static void
fd_clear(struct pipe_context *pctx, unsigned buffers,
const union pipe_color_union *color, double depth, unsigned stencil)
{
struct fd_context *ctx = fd_context(pctx);
struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
unsigned cleared_buffers;
/* for bookkeeping about which buffers have been cleared (and thus
* can fully or partially skip mem2gmem) we need to ignore buffers
* that have already had a draw, in case apps do silly things like
* clear after draw (ie. if you only clear the color buffer, but
* something like alpha-test causes side effects from the draw in
* the depth buffer, etc)
*/
cleared_buffers = buffers & (FD_BUFFER_ALL & ~ctx->restore);
/* do we have full-screen scissor? */
if (!memcmp(scissor, &ctx->disabled_scissor, sizeof(*scissor))) {
ctx->cleared |= cleared_buffers;
} else {
ctx->partial_cleared |= cleared_buffers;
if (cleared_buffers & PIPE_CLEAR_COLOR)
ctx->cleared_scissor.color = *scissor;
if (cleared_buffers & PIPE_CLEAR_DEPTH)
ctx->cleared_scissor.depth = *scissor;
if (cleared_buffers & PIPE_CLEAR_STENCIL)
ctx->cleared_scissor.stencil = *scissor;
}
ctx->resolve |= buffers;
ctx->needs_flush = true;
if (buffers & PIPE_CLEAR_COLOR)
fd_resource(pfb->cbufs[0]->texture)->dirty = true;
if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
fd_resource(pfb->zsbuf->texture)->dirty = true;
ctx->gmem_reason |= FD_GMEM_CLEARS_DEPTH_STENCIL;
}
DBG("%x depth=%f, stencil=%u (%s/%s)", buffers, depth, stencil,
util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
util_format_short_name(pipe_surface_format(pfb->zsbuf)));
fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_CLEAR);
ctx->clear(ctx, buffers, color, depth, stencil);
ctx->dirty |= FD_DIRTY_ZSA |
FD_DIRTY_VIEWPORT |
FD_DIRTY_RASTERIZER |
FD_DIRTY_SAMPLE_MASK |
FD_DIRTY_PROG |
FD_DIRTY_CONSTBUF |
FD_DIRTY_BLEND;
if (fd_mesa_debug & FD_DBG_DCLEAR)
ctx->dirty = 0xffffffff;
}
static void
fd_rasterizer_state_bind(struct pipe_context *pctx, void *hwcso)
{
struct fd_context *ctx = fd_context(pctx);
struct pipe_scissor_state *old_scissor = fd_context_get_scissor(ctx);
ctx->rasterizer = hwcso;
ctx->dirty |= FD_DIRTY_RASTERIZER;
/* if scissor enable bit changed we need to mark scissor
* state as dirty as well:
* NOTE: we can do a shallow compare, since we only care
* if it changed to/from &ctx->disable_scissor
*/
if (old_scissor != fd_context_get_scissor(ctx))
ctx->dirty |= FD_DIRTY_SCISSOR;
}
static void
fd_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
{
struct fd_context *ctx = fd_context(pctx);
struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
unsigned i, buffers = 0;
/* if we supported transform feedback, we'd have to disable this: */
if (((scissor->maxx - scissor->minx) *
(scissor->maxy - scissor->miny)) == 0) {
return;
}
ctx->needs_flush = true;
/*
* Figure out the buffers/features we need:
*/
if (fd_depth_enabled(ctx)) {
buffers |= FD_BUFFER_DEPTH;
fd_resource(pfb->zsbuf->texture)->dirty = true;
ctx->gmem_reason |= FD_GMEM_DEPTH_ENABLED;
}
if (fd_stencil_enabled(ctx)) {
buffers |= FD_BUFFER_STENCIL;
fd_resource(pfb->zsbuf->texture)->dirty = true;
ctx->gmem_reason |= FD_GMEM_STENCIL_ENABLED;
}
if (fd_logicop_enabled(ctx))
ctx->gmem_reason |= FD_GMEM_LOGICOP_ENABLED;
for (i = 0; i < pfb->nr_cbufs; i++) {
struct pipe_resource *surf = pfb->cbufs[i]->texture;
fd_resource(surf)->dirty = true;
buffers |= FD_BUFFER_COLOR;
if (surf->nr_samples > 1)
ctx->gmem_reason |= FD_GMEM_MSAA_ENABLED;
if (fd_blend_enabled(ctx, i))
ctx->gmem_reason |= FD_GMEM_BLEND_ENABLED;
}
ctx->num_draws++;
/* any buffers that haven't been cleared, we need to restore: */
ctx->restore |= buffers & (FD_BUFFER_ALL & ~ctx->cleared);
/* and any buffers used, need to be resolved: */
ctx->resolve |= buffers;
ctx->draw(ctx, info);
}
static bool
fd6_clear(struct fd_context *ctx, unsigned buffers,
const union pipe_color_union *color, double depth, unsigned stencil)
{
struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
struct fd_ringbuffer *ring = ctx->batch->draw;
if ((buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) &&
is_z32(pfb->zsbuf->format))
return false;
fd6_emit_render_cntl(ctx, true, false);
OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
OUT_RING(ring, A6XX_RB_BLIT_SCISSOR_TL_X(scissor->minx) |
A6XX_RB_BLIT_SCISSOR_TL_Y(scissor->miny));
OUT_RING(ring, A6XX_RB_BLIT_SCISSOR_BR_X(scissor->maxx - 1) |
A6XX_RB_BLIT_SCISSOR_BR_Y(scissor->maxy - 1));
if (buffers & PIPE_CLEAR_COLOR) {
for (int i = 0; i < pfb->nr_cbufs; i++) {
union util_color uc = {0};
if (!pfb->cbufs[i])
continue;
if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
continue;
enum pipe_format pfmt = pfb->cbufs[i]->format;
// XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
union pipe_color_union swapped;
switch (fd6_pipe2swap(pfmt)) {
case WZYX:
swapped.ui[0] = color->ui[0];
swapped.ui[1] = color->ui[1];
swapped.ui[2] = color->ui[2];
swapped.ui[3] = color->ui[3];
break;
case WXYZ:
swapped.ui[2] = color->ui[0];
swapped.ui[1] = color->ui[1];
swapped.ui[0] = color->ui[2];
swapped.ui[3] = color->ui[3];
break;
case ZYXW:
swapped.ui[3] = color->ui[0];
swapped.ui[0] = color->ui[1];
swapped.ui[1] = color->ui[2];
swapped.ui[2] = color->ui[3];
break;
case XYZW:
swapped.ui[3] = color->ui[0];
swapped.ui[2] = color->ui[1];
swapped.ui[1] = color->ui[2];
swapped.ui[0] = color->ui[3];
break;
}
if (util_format_is_pure_uint(pfmt)) {
util_format_write_4ui(pfmt, swapped.ui, 0, &uc, 0, 0, 0, 1, 1);
} else if (util_format_is_pure_sint(pfmt)) {
util_format_write_4i(pfmt, swapped.i, 0, &uc, 0, 0, 0, 1, 1);
} else {
util_pack_color(swapped.f, pfmt, &uc);
}
OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
OUT_RINGP(ring, i, &ctx->batch->gmem_patches);
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
OUT_RING(ring, 0);
OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
OUT_RING(ring, uc.ui[0]);
OUT_RING(ring, uc.ui[1]);
OUT_RING(ring, uc.ui[2]);
OUT_RING(ring, uc.ui[3]);
fd6_emit_blit(ctx->batch, ring);
}
}
if (pfb->zsbuf && (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL))) {
enum pipe_format pfmt = pfb->zsbuf->format;
uint32_t clear = util_pack_z_stencil(pfmt, depth, stencil);
uint32_t mask = 0;
if (buffers & PIPE_CLEAR_DEPTH)
mask |= 0x1;
if (buffers & PIPE_CLEAR_STENCIL)
mask |= 0x2;
OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
// XXX UNK0 for separate stencil ??
A6XX_RB_BLIT_INFO_DEPTH |
A6XX_RB_BLIT_INFO_CLEAR_MASK(mask));
OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
OUT_RINGP(ring, MAX_RENDER_TARGETS, &ctx->batch->gmem_patches);
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
OUT_RING(ring, 0);
OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
OUT_RING(ring, clear);
fd6_emit_blit(ctx->batch, ring);
if (pfb->zsbuf && (buffers & PIPE_CLEAR_DEPTH)) {
struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture);
if (zsbuf->lrz) {
zsbuf->lrz_valid = true;
fd6_clear_lrz(ctx->batch, zsbuf, depth);
}
}
}
return true;
}
static void
fd_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
{
struct fd_context *ctx = fd_context(pctx);
struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
unsigned i, buffers = 0;
/* if we supported transform feedback, we'd have to disable this: */
if (((scissor->maxx - scissor->minx) *
(scissor->maxy - scissor->miny)) == 0) {
return;
}
/* emulate unsupported primitives: */
if (!fd_supported_prim(ctx, info->mode)) {
util_primconvert_save_index_buffer(ctx->primconvert, &ctx->indexbuf);
util_primconvert_save_rasterizer_state(ctx->primconvert, ctx->rasterizer);
util_primconvert_draw_vbo(ctx->primconvert, info);
return;
}
ctx->needs_flush = true;
/*
* Figure out the buffers/features we need:
*/
if (fd_depth_enabled(ctx)) {
buffers |= FD_BUFFER_DEPTH;
fd_resource(pfb->zsbuf->texture)->dirty = true;
ctx->gmem_reason |= FD_GMEM_DEPTH_ENABLED;
}
if (fd_stencil_enabled(ctx)) {
buffers |= FD_BUFFER_STENCIL;
fd_resource(pfb->zsbuf->texture)->dirty = true;
ctx->gmem_reason |= FD_GMEM_STENCIL_ENABLED;
}
if (fd_logicop_enabled(ctx))
ctx->gmem_reason |= FD_GMEM_LOGICOP_ENABLED;
for (i = 0; i < pfb->nr_cbufs; i++) {
struct pipe_resource *surf;
if (!pfb->cbufs[i])
continue;
surf = pfb->cbufs[i]->texture;
fd_resource(surf)->dirty = true;
buffers |= FD_BUFFER_COLOR;
if (surf->nr_samples > 1)
ctx->gmem_reason |= FD_GMEM_MSAA_ENABLED;
if (fd_blend_enabled(ctx, i))
ctx->gmem_reason |= FD_GMEM_BLEND_ENABLED;
}
ctx->num_draws++;
ctx->stats.draw_calls++;
ctx->stats.prims_emitted +=
u_reduced_prims_for_vertices(info->mode, info->count);
/* any buffers that haven't been cleared, we need to restore: */
ctx->restore |= buffers & (FD_BUFFER_ALL & ~ctx->cleared);
/* and any buffers used, need to be resolved: */
ctx->resolve |= buffers;
ctx->draw(ctx, info);
}
void
fd2_emit_state(struct fd_context *ctx, uint32_t dirty)
{
struct fd2_blend_stateobj *blend = fd2_blend_stateobj(ctx->blend);
struct fd2_zsa_stateobj *zsa = fd2_zsa_stateobj(ctx->zsa);
struct fd_ringbuffer *ring = ctx->ring;
/* NOTE: we probably want to eventually refactor this so each state
* object handles emitting it's own state.. although the mapping of
* state to registers is not always orthogonal, sometimes a single
* register contains bitfields coming from multiple state objects,
* so not sure the best way to deal with that yet.
*/
if (dirty & FD_DIRTY_SAMPLE_MASK) {
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
OUT_RING(ring, ctx->sample_mask);
}
if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
struct pipe_stencil_ref *sr = &ctx->stencil_ref;
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
OUT_RING(ring, zsa->rb_depthcontrol);
OUT_PKT3(ring, CP_SET_CONSTANT, 4);
OUT_RING(ring, CP_REG(REG_A2XX_RB_STENCILREFMASK_BF));
OUT_RING(ring, zsa->rb_stencilrefmask_bf |
A2XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[1]));
OUT_RING(ring, zsa->rb_stencilrefmask |
A2XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
OUT_RING(ring, zsa->rb_alpha_ref);
}
if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_FRAMEBUFFER)) {
struct fd2_rasterizer_stateobj *rasterizer =
fd2_rasterizer_stateobj(ctx->rasterizer);
OUT_PKT3(ring, CP_SET_CONSTANT, 3);
OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
OUT_RING(ring, rasterizer->pa_cl_clip_cntl);
OUT_RING(ring, rasterizer->pa_su_sc_mode_cntl |
A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE);
OUT_PKT3(ring, CP_SET_CONSTANT, 5);
OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_POINT_SIZE));
OUT_RING(ring, rasterizer->pa_su_point_size);
OUT_RING(ring, rasterizer->pa_su_point_minmax);
OUT_RING(ring, rasterizer->pa_su_line_cntl);
OUT_RING(ring, rasterizer->pa_sc_line_stipple);
OUT_PKT3(ring, CP_SET_CONSTANT, 6);
OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_VTX_CNTL));
OUT_RING(ring, rasterizer->pa_su_vtx_cntl);
OUT_RING(ring, fui(1.0)); /* PA_CL_GB_VERT_CLIP_ADJ */
OUT_RING(ring, fui(1.0)); /* PA_CL_GB_VERT_DISC_ADJ */
OUT_RING(ring, fui(1.0)); /* PA_CL_GB_HORZ_CLIP_ADJ */
OUT_RING(ring, fui(1.0)); /* PA_CL_GB_HORZ_DISC_ADJ */
}
if (dirty & FD_DIRTY_SCISSOR) {
struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
OUT_PKT3(ring, CP_SET_CONSTANT, 3);
OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
OUT_RING(ring, xy2d(scissor->minx, /* PA_SC_WINDOW_SCISSOR_TL */
scissor->miny));
OUT_RING(ring, xy2d(scissor->maxx, /* PA_SC_WINDOW_SCISSOR_BR */
scissor->maxy));
ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
}
if (dirty & FD_DIRTY_VIEWPORT) {
OUT_PKT3(ring, CP_SET_CONSTANT, 7);
OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE));
OUT_RING(ring, fui(ctx->viewport.scale[0])); /* PA_CL_VPORT_XSCALE */
OUT_RING(ring, fui(ctx->viewport.translate[0])); /* PA_CL_VPORT_XOFFSET */
OUT_RING(ring, fui(ctx->viewport.scale[1])); /* PA_CL_VPORT_YSCALE */
OUT_RING(ring, fui(ctx->viewport.translate[1])); /* PA_CL_VPORT_YOFFSET */
OUT_RING(ring, fui(ctx->viewport.scale[2])); /* PA_CL_VPORT_ZSCALE */
OUT_RING(ring, fui(ctx->viewport.translate[2])); /* PA_CL_VPORT_ZOFFSET */
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT |
A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA |
A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA |
A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA);
}
if (dirty & (FD_DIRTY_PROG | FD_DIRTY_VTXSTATE | FD_DIRTY_TEXSTATE)) {
fd2_program_validate(ctx);
fd2_program_emit(ring, &ctx->prog);
}
if (dirty & (FD_DIRTY_PROG | FD_DIRTY_CONSTBUF)) {
emit_constants(ring, VS_CONST_BASE * 4,
&ctx->constbuf[PIPE_SHADER_VERTEX],
(dirty & FD_DIRTY_PROG) ? ctx->prog.vp : NULL);
emit_constants(ring, PS_CONST_BASE * 4,
&ctx->constbuf[PIPE_SHADER_FRAGMENT],
(dirty & FD_DIRTY_PROG) ? ctx->prog.fp : NULL);
}
if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_ZSA)) {
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
OUT_RING(ring, zsa->rb_colorcontrol | blend->rb_colorcontrol);
}
if (dirty & FD_DIRTY_BLEND) {
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL));
OUT_RING(ring, blend->rb_blendcontrol);
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK));
OUT_RING(ring, blend->rb_colormask);
}
if (dirty & (FD_DIRTY_VERTTEX | FD_DIRTY_FRAGTEX | FD_DIRTY_PROG))
emit_textures(ring, ctx);
ctx->dirty &= ~dirty;
}
void
fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
struct fd4_emit *emit)
{
struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
struct ir3_shader_variant *fp = fd4_emit_get_fp(emit);
uint32_t dirty = emit->dirty;
emit_marker(ring, 5);
if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && !emit->key.binning_pass) {
uint32_t val = fd4_zsa_stateobj(ctx->zsa)->rb_render_control;
/* I suppose if we needed to (which I don't *think* we need
* to), we could emit this for binning pass too. But we
* would need to keep a different patch-list for binning
* vs render pass.
*/
OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
OUT_RINGP(ring, val, &fd4_context(ctx)->rbrc_patches);
}
if (dirty & FD_DIRTY_ZSA) {
struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
OUT_RING(ring, zsa->rb_alpha_control);
OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
OUT_RING(ring, zsa->rb_stencil_control);
OUT_RING(ring, zsa->rb_stencil_control2);
}
if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
struct pipe_stencil_ref *sr = &ctx->stencil_ref;
OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
OUT_RING(ring, zsa->rb_stencilrefmask |
A4XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
OUT_RING(ring, zsa->rb_stencilrefmask_bf |
A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
}
if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
bool fragz = fp->has_kill | fp->writes_pos;
OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
OUT_RING(ring, zsa->rb_depth_control |
COND(fragz, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE));
/* maybe this register/bitfield needs a better name.. this
* appears to be just disabling early-z
*/
OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
OUT_RING(ring, zsa->gras_alpha_control |
COND(fragz, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE));
}
if (dirty & FD_DIRTY_RASTERIZER) {
struct fd4_rasterizer_stateobj *rasterizer =
fd4_rasterizer_stateobj(ctx->rasterizer);
OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
OUT_RING(ring, rasterizer->gras_su_mode_control |
A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
OUT_PKT0(ring, REG_A4XX_GRAS_SU_POINT_MINMAX, 2);
OUT_RING(ring, rasterizer->gras_su_point_minmax);
OUT_RING(ring, rasterizer->gras_su_point_size);
OUT_PKT0(ring, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
}
/* NOTE: since primitive_restart is not actually part of any
* state object, we need to make sure that we always emit
* PRIM_VTX_CNTL.. either that or be more clever and detect
* when it changes.
*/
if (emit->info) {
const struct pipe_draw_info *info = emit->info;
uint32_t val = fd4_rasterizer_stateobj(ctx->rasterizer)
->pc_prim_vtx_cntl;
if (info->indexed && info->primitive_restart)
val |= A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
val |= COND(vp->writes_psize, A4XX_PC_PRIM_VTX_CNTL_PSIZE);
if (fp->total_in > 0) {
uint32_t varout = align(fp->total_in, 16) / 16;
if (varout > 1)
varout = align(varout, 2);
val |= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout);
}
OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
OUT_RING(ring, val);
OUT_RING(ring, 0x12); /* XXX UNKNOWN_21C5 */
}
if (dirty & FD_DIRTY_SCISSOR) {
struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
}
if (dirty & FD_DIRTY_VIEWPORT) {
fd_wfi(ctx, ring);
OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
}
if (dirty & FD_DIRTY_PROG)
fd4_program_emit(ring, emit);
if ((dirty & (FD_DIRTY_PROG | FD_DIRTY_CONSTBUF)) &&
/* evil hack to deal sanely with clear path: */
(emit->prog == &ctx->prog)) {
fd_wfi(ctx, ring);
emit_constants(ring, SB_VERT_SHADER,
&ctx->constbuf[PIPE_SHADER_VERTEX],
vp, emit->prog->dirty & FD_SHADER_DIRTY_VP);
if (!emit->key.binning_pass) {
emit_constants(ring, SB_FRAG_SHADER,
&ctx->constbuf[PIPE_SHADER_FRAGMENT],
fp, emit->prog->dirty & FD_SHADER_DIRTY_FP);
}
}
/* emit driver params every time */
if (emit->info && emit->prog == &ctx->prog) {
uint32_t vertex_params[4] = {
emit->info->indexed ? emit->info->index_bias : emit->info->start,
0,
0,
0
};
if (vp->constlen >= vp->first_driver_param + 4) {
fd4_emit_constant(ring, SB_VERT_SHADER,
(vp->first_driver_param + 4) * 4,
0, 4, vertex_params, NULL);
}
}
if ((dirty & FD_DIRTY_BLEND) && ctx->blend) {
struct fd4_blend_stateobj *blend = fd4_blend_stateobj(ctx->blend);
uint32_t i;
for (i = 0; i < 8; i++) {
OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
OUT_RING(ring, blend->rb_mrt[i].control);
OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
OUT_RING(ring, blend->rb_mrt[i].blend_control);
}
OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
OUT_RING(ring, blend->rb_fs_output |
A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
}
if (dirty & FD_DIRTY_BLEND_COLOR) {
struct pipe_blend_color *bcolor = &ctx->blend_color;
OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4);
OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
A4XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
A4XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
A4XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
A4XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
}
if (dirty & FD_DIRTY_VERTTEX) {
if (vp->has_samp)
emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
else
dirty &= ~FD_DIRTY_VERTTEX;
}
if (dirty & FD_DIRTY_FRAGTEX) {
if (fp->has_samp)
emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
else
dirty &= ~FD_DIRTY_FRAGTEX;
}
ctx->dirty &= ~dirty;
}
static void
fd_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
{
struct fd_context *ctx = fd_context(pctx);
struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
unsigned i, prims, buffers = 0;
/* if we supported transform feedback, we'd have to disable this: */
if (((scissor->maxx - scissor->minx) *
(scissor->maxy - scissor->miny)) == 0) {
return;
}
/* TODO: push down the region versions into the tiles */
if (!fd_render_condition_check(pctx))
return;
/* emulate unsupported primitives: */
if (!fd_supported_prim(ctx, info->mode)) {
if (ctx->streamout.num_targets > 0)
debug_error("stream-out with emulated prims");
util_primconvert_save_index_buffer(ctx->primconvert, &ctx->indexbuf);
util_primconvert_save_rasterizer_state(ctx->primconvert, ctx->rasterizer);
util_primconvert_draw_vbo(ctx->primconvert, info);
return;
}
ctx->needs_flush = true;
/*
* Figure out the buffers/features we need:
*/
if (fd_depth_enabled(ctx)) {
buffers |= FD_BUFFER_DEPTH;
resource_written(ctx, pfb->zsbuf->texture);
ctx->gmem_reason |= FD_GMEM_DEPTH_ENABLED;
}
if (fd_stencil_enabled(ctx)) {
buffers |= FD_BUFFER_STENCIL;
resource_written(ctx, pfb->zsbuf->texture);
ctx->gmem_reason |= FD_GMEM_STENCIL_ENABLED;
}
if (fd_logicop_enabled(ctx))
ctx->gmem_reason |= FD_GMEM_LOGICOP_ENABLED;
for (i = 0; i < pfb->nr_cbufs; i++) {
struct pipe_resource *surf;
if (!pfb->cbufs[i])
continue;
surf = pfb->cbufs[i]->texture;
resource_written(ctx, surf);
buffers |= PIPE_CLEAR_COLOR0 << i;
if (surf->nr_samples > 1)
ctx->gmem_reason |= FD_GMEM_MSAA_ENABLED;
if (fd_blend_enabled(ctx, i))
ctx->gmem_reason |= FD_GMEM_BLEND_ENABLED;
}
/* Skip over buffer 0, that is sent along with the command stream */
for (i = 1; i < PIPE_MAX_CONSTANT_BUFFERS; i++) {
resource_read(ctx, ctx->constbuf[PIPE_SHADER_VERTEX].cb[i].buffer);
resource_read(ctx, ctx->constbuf[PIPE_SHADER_FRAGMENT].cb[i].buffer);
}
/* Mark VBOs as being read */
for (i = 0; i < ctx->vtx.vertexbuf.count; i++) {
assert(!ctx->vtx.vertexbuf.vb[i].user_buffer);
resource_read(ctx, ctx->vtx.vertexbuf.vb[i].buffer);
}
/* Mark index buffer as being read */
resource_read(ctx, ctx->indexbuf.buffer);
/* Mark textures as being read */
for (i = 0; i < ctx->verttex.num_textures; i++)
if (ctx->verttex.textures[i])
resource_read(ctx, ctx->verttex.textures[i]->texture);
for (i = 0; i < ctx->fragtex.num_textures; i++)
if (ctx->fragtex.textures[i])
resource_read(ctx, ctx->fragtex.textures[i]->texture);
/* Mark streamout buffers as being written.. */
for (i = 0; i < ctx->streamout.num_targets; i++)
if (ctx->streamout.targets[i])
resource_written(ctx, ctx->streamout.targets[i]->buffer);
ctx->num_draws++;
prims = u_reduced_prims_for_vertices(info->mode, info->count);
ctx->stats.draw_calls++;
/* TODO prims_emitted should be clipped when the stream-out buffer is
* not large enough. See max_tf_vtx().. probably need to move that
* into common code. Although a bit more annoying since a2xx doesn't
* use ir3 so no common way to get at the pipe_stream_output_info
* which is needed for this calculation.
*/
if (ctx->streamout.num_targets > 0)
ctx->stats.prims_emitted += prims;
ctx->stats.prims_generated += prims;
/* any buffers that haven't been cleared yet, we need to restore: */
ctx->restore |= buffers & (FD_BUFFER_ALL & ~ctx->cleared);
/* and any buffers used, need to be resolved: */
ctx->resolve |= buffers;
DBG("%x num_draws=%u (%s/%s)", buffers, ctx->num_draws,
util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
util_format_short_name(pipe_surface_format(pfb->zsbuf)));
fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_DRAW);
ctx->draw_vbo(ctx, info);
for (i = 0; i < ctx->streamout.num_targets; i++)
ctx->streamout.offsets[i] += info->count;
if (fd_mesa_debug & FD_DBG_DDRAW)
ctx->dirty = 0xffffffff;
/* if an app (or, well, piglit test) does many thousands of draws
* without flush (or anything which implicitly flushes, like
* changing render targets), we can exceed the ringbuffer size.
* Since we don't currently have a sane way to wrapparound, and
* we use the same buffer for both draw and tiling commands, for
* now we need to do this hack and trigger flush if we are running
* low on remaining space for cmds:
*/
if (((ctx->ring->cur - ctx->ring->start) >
(ctx->ring->size/4 - FD_TILING_COMMANDS_DWORDS)) ||
(fd_mesa_debug & FD_DBG_FLUSH))
fd_context_render(pctx);
}
static void
fd_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
{
struct fd_context *ctx = fd_context(pctx);
struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
unsigned i, buffers = 0;
/* if we supported transform feedback, we'd have to disable this: */
if (((scissor->maxx - scissor->minx) *
(scissor->maxy - scissor->miny)) == 0) {
return;
}
/* emulate unsupported primitives: */
if (!fd_supported_prim(ctx, info->mode)) {
util_primconvert_save_index_buffer(ctx->primconvert, &ctx->indexbuf);
util_primconvert_save_rasterizer_state(ctx->primconvert, ctx->rasterizer);
util_primconvert_draw_vbo(ctx->primconvert, info);
return;
}
ctx->needs_flush = true;
/*
* Figure out the buffers/features we need:
*/
if (fd_depth_enabled(ctx)) {
buffers |= FD_BUFFER_DEPTH;
fd_resource(pfb->zsbuf->texture)->dirty = true;
ctx->gmem_reason |= FD_GMEM_DEPTH_ENABLED;
}
if (fd_stencil_enabled(ctx)) {
buffers |= FD_BUFFER_STENCIL;
fd_resource(pfb->zsbuf->texture)->dirty = true;
ctx->gmem_reason |= FD_GMEM_STENCIL_ENABLED;
}
if (fd_logicop_enabled(ctx))
ctx->gmem_reason |= FD_GMEM_LOGICOP_ENABLED;
for (i = 0; i < pfb->nr_cbufs; i++) {
struct pipe_resource *surf;
if (!pfb->cbufs[i])
continue;
surf = pfb->cbufs[i]->texture;
fd_resource(surf)->dirty = true;
buffers |= FD_BUFFER_COLOR;
if (surf->nr_samples > 1)
ctx->gmem_reason |= FD_GMEM_MSAA_ENABLED;
if (fd_blend_enabled(ctx, i))
ctx->gmem_reason |= FD_GMEM_BLEND_ENABLED;
}
ctx->num_draws++;
ctx->stats.draw_calls++;
ctx->stats.prims_emitted +=
u_reduced_prims_for_vertices(info->mode, info->count);
/* any buffers that haven't been cleared yet, we need to restore: */
ctx->restore |= buffers & (FD_BUFFER_ALL & ~ctx->cleared);
/* and any buffers used, need to be resolved: */
ctx->resolve |= buffers;
DBG("%x num_draws=%u (%s/%s)", buffers, ctx->num_draws,
util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
util_format_short_name(pipe_surface_format(pfb->zsbuf)));
fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_DRAW);
ctx->draw_vbo(ctx, info);
/* if an app (or, well, piglit test) does many thousands of draws
* without flush (or anything which implicitly flushes, like
* changing render targets), we can exceed the ringbuffer size.
* Since we don't currently have a sane way to wrapparound, and
* we use the same buffer for both draw and tiling commands, for
* now we need to do this hack and trigger flush if we are running
* low on remaining space for cmds:
*/
if (((ctx->ring->cur - ctx->ring->start) >
(ctx->ring->size/4 - FD_TILING_COMMANDS_DWORDS)) ||
(fd_mesa_debug & FD_DBG_FLUSH))
fd_context_render(pctx);
}
