static void mt7621_rxvlan_config(bool enable) { if (enable) fe_w32(1, MT7621_CDMP_EG_CTRL); else fe_w32(0, MT7621_CDMP_EG_CTRL); }
static void mt7621_set_mac(struct fe_priv *priv, unsigned char *mac) { unsigned long flags; spin_lock_irqsave(&priv->page_lock, flags); fe_w32((mac[0] << 8) | mac[1], GSW_REG_GDMA1_MAC_ADRH); fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], GSW_REG_GDMA1_MAC_ADRL); spin_unlock_irqrestore(&priv->page_lock, flags); }
static void mt7620_rxcsum_config(bool enable) { if (enable) fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN | GDMA_TCS_EN | GDMA_UCS_EN), MT7620A_GDMA1_FWD_CFG); else fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN | GDMA_TCS_EN | GDMA_UCS_EN), MT7620A_GDMA1_FWD_CFG); }
static void mt7620_txcsum_config(bool enable) { if (enable) fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN | CDMA_UCS_EN | CDMA_TCS_EN), MT7620A_CDMA_CSG_CFG); else fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN | CDMA_UCS_EN | CDMA_TCS_EN), MT7620A_CDMA_CSG_CFG); }
static void rt5350_rxcsum_config(bool enable) { if (enable) fe_w32(fe_r32(RT5350_SDM_CFG) | (RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN), RT5350_SDM_CFG); else fe_w32(fe_r32(RT5350_SDM_CFG) & ~(RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN), RT5350_SDM_CFG); }
static int mt7621_fwd_config(struct fe_priv *priv) { struct net_device *dev = priv_netdev(priv); fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~0xffff, MT7620A_GDMA1_FWD_CFG); mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM)); mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM)); return 0; }
static int mt7621_fwd_config(struct fe_priv *priv) { struct net_device *dev = priv_netdev(priv); fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~0xffff, MT7620A_GDMA1_FWD_CFG); /* mt7621 doesn't have txcsum config */ mt7621_rxcsum_config((dev->features & NETIF_F_RXCSUM)); mt7621_rxvlan_config(priv->flags & FE_FLAG_RX_VLAN_CTAG); return 0; }
static int rt3883_fwd_config(struct fe_priv *priv) { int ret; ret = fe_set_clock_cycle(priv); if (ret) return ret; fe_fwd_config(priv); fe_w32(FE_PSE_FQFC_CFG_256Q, FE_PSE_FQ_CFG); fe_csum_config(priv); return ret; }
static int rt3050_fwd_config(struct fe_priv *priv) { int ret; if (ralink_soc != RT305X_SOC_RT3052) { ret = fe_set_clock_cycle(priv); if (ret) return ret; } fe_fwd_config(priv); if (ralink_soc != RT305X_SOC_RT3352) fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG); fe_csum_config(priv); return 0; }