// // Interrupt processing // static void fec_eth_int(struct eth_drv_sc *sc) { struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private; unsigned long iEvent; while ((iEvent = qi->fcc_reg->fcc_fcce) != 0){ // Writing 1's clear fcce, Writing 0's have no effect qi->fcc_reg->fcc_fcce = iEvent; // Tx Done or Tx Error if ( iEvent & (FEC_EV_TXB | FEC_EV_TXE) ) { fec_eth_TxEvent(sc, iEvent); } // Complete or non-complete frame receive if (iEvent & (FEC_EV_RXF | FEC_EV_RXB) ) { fec_eth_RxEvent(sc); } } }
// // Interrupt processing // static void fec_eth_int(struct eth_drv_sc *sc) { struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private; unsigned long event; while ((event = qi->fec->iEvent) != 0) { if ((event & iEvent_TFINT) != 0) { fec_eth_TxEvent(sc); } if ((event & iEvent_RFINT) != 0) { fec_eth_RxEvent(sc); } qi->fec->iEvent = event; // Reset the bits we handled } }