static int fec_init(struct eth_device *dev, bd_t *bd)
#endif
{
#ifdef CONFIG_DM_ETH
struct fec_priv *fec = dev_get_priv(dev);
#else
struct fec_priv *fec = (struct fec_priv *)dev->priv;
#endif
uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
int i;
/* Initialize MAC address */
#ifdef CONFIG_DM_ETH
fecmxc_set_hwaddr(dev);
#else
fec_set_hwaddr(dev);
#endif
/* Setup transmit descriptors, there are two in total. */
fec_tbd_init(fec);
/* Setup receive descriptors. */
fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
fec_reg_setup(fec);
if (fec->xcv_type != SEVENWIRE)
fec_mii_setspeed(fec->bus->priv);
/* Set Opcode/Pause Duration Register */
writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
writel(0x2, &fec->eth->x_wmrk);
/* Set multicast address filter */
writel(0x00000000, &fec->eth->gaddr1);
writel(0x00000000, &fec->eth->gaddr2);
/* Do not access reserved register for i.MX6UL */
if (!is_mx6ul()) {
/* clear MIB RAM */
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
writel(0, i);
/* FIFO receive start register */
writel(0x520, &fec->eth->r_fstart);
}
/* size and address of each buffer */
writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
#ifndef CONFIG_PHYLIB
if (fec->xcv_type != SEVENWIRE)
miiphy_restart_aneg(dev);
#endif
fec_open(dev);
return 0;
}
static int fecmxc_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct fec_priv *priv = dev_get_priv(dev);
struct mii_dev *bus = NULL;
int dev_id = -1;
uint32_t start;
int ret;
ret = fec_alloc_descs(priv);
if (ret)
return ret;
bus = fec_get_miibus((uint32_t)priv->eth, dev_id);
if (!bus)
goto err_mii;
priv->bus = bus;
priv->xcv_type = CONFIG_FEC_XCV_TYPE;
priv->interface = pdata->phy_interface;
ret = fec_phy_init(priv, dev);
if (ret)
goto err_phy;
/* Reset chip. */
writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
&priv->eth->ecntrl);
start = get_timer(0);
while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
printf("FEC MXC: Timeout reseting chip\n");
goto err_timeout;
}
udelay(10);
}
fec_reg_setup(priv);
fec_set_dev_name((char *)dev->name, dev_id);
priv->dev_id = (dev_id == -1) ? 0 : dev_id;
return 0;
err_timeout:
free(priv->phydev);
err_phy:
mdio_unregister(bus);
free(bus);
err_mii:
fec_free_descs(priv);
return ret;
}
static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
struct mii_dev *bus, int phy_id)
#endif
{
struct eth_device *edev;
struct fec_priv *fec;
unsigned char ethaddr[6];
uint32_t start;
int ret = 0;
/* create and fill edev struct */
edev = (struct eth_device *)malloc(sizeof(struct eth_device));
if (!edev) {
puts("fec_mxc: not enough malloc memory for eth_device\n");
ret = -ENOMEM;
goto err1;
}
fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
if (!fec) {
puts("fec_mxc: not enough malloc memory for fec_priv\n");
ret = -ENOMEM;
goto err2;
}
memset(edev, 0, sizeof(*edev));
memset(fec, 0, sizeof(*fec));
ret = fec_alloc_descs(fec);
if (ret)
goto err3;
edev->priv = fec;
edev->init = fec_init;
edev->send = fec_send;
edev->recv = fec_recv;
edev->halt = fec_halt;
edev->write_hwaddr = fec_set_hwaddr;
fec->eth = (struct ethernet_regs *)base_addr;
fec->bd = bd;
fec->xcv_type = CONFIG_FEC_XCV_TYPE;
/* Reset chip. */
writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
start = get_timer(0);
while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
printf("FEC MXC: Timeout reseting chip\n");
goto err4;
}
udelay(10);
}
fec_reg_setup(fec);
fec_set_dev_name(edev->name, dev_id);
fec->dev_id = (dev_id == -1) ? 0 : dev_id;
fec->bus = bus;
fec_mii_setspeed(bus->priv);
#ifdef CONFIG_PHYLIB
fec->phydev = phydev;
phy_connect_dev(phydev, edev);
/* Configure phy */
phy_config(phydev);
#else
fec->phy_id = phy_id;
#endif
eth_register(edev);
if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
memcpy(edev->enetaddr, ethaddr, 6);
if (!getenv("ethaddr"))
eth_setenv_enetaddr("ethaddr", ethaddr);
}
return ret;
err4:
fec_free_descs(fec);
err3:
free(fec);
err2:
free(edev);
err1:
return ret;
}
static int fec_init(struct eth_device *dev, bd_t* bd)
{
struct fec_priv *fec = (struct fec_priv *)dev->priv;
uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
uint32_t size;
int i, ret;
/* Initialize MAC address */
fec_set_hwaddr(dev);
/*
* Allocate transmit descriptors, there are two in total. This
* allocation respects cache alignment.
*/
if (!fec->tbd_base) {
size = roundup(2 * sizeof(struct fec_bd),
ARCH_DMA_MINALIGN);
fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
if (!fec->tbd_base) {
ret = -ENOMEM;
goto err1;
}
memset(fec->tbd_base, 0, size);
fec_tbd_init(fec);
}
/*
* Allocate receive descriptors. This allocation respects cache
* alignment.
*/
if (!fec->rbd_base) {
size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
ARCH_DMA_MINALIGN);
fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
if (!fec->rbd_base) {
ret = -ENOMEM;
goto err2;
}
memset(fec->rbd_base, 0, size);
/*
* Initialize RxBD ring
*/
if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
ret = -ENOMEM;
goto err3;
}
flush_dcache_range((unsigned)fec->rbd_base,
(unsigned)fec->rbd_base + size);
}
fec_reg_setup(fec);
if (fec->xcv_type != SEVENWIRE)
fec_mii_setspeed(fec->bus->priv);
/*
* Set Opcode/Pause Duration Register
*/
writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
writel(0x2, &fec->eth->x_wmrk);
/*
* Set multicast address filter
*/
writel(0x00000000, &fec->eth->gaddr1);
writel(0x00000000, &fec->eth->gaddr2);
/* clear MIB RAM */
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
writel(0, i);
/* FIFO receive start register */
writel(0x520, &fec->eth->r_fstart);
/* size and address of each buffer */
writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
#ifndef CONFIG_PHYLIB
if (fec->xcv_type != SEVENWIRE)
miiphy_restart_aneg(dev);
#endif
fec_open(dev);
return 0;
err3:
free(fec->rbd_base);
err2:
free(fec->tbd_base);
err1:
return ret;
}
