Пример #1
0
int		select_loop(int svr_sock, t_select *slt_par, t_game *game)
{
  t_svr_vector	vec;
  int		err;

  slt_cont = 1;
  init_vector(&vec, slt_par);
  while (slt_cont)
    {
      err = select(slt_par->fd_max, &(slt_par->fd_read), NULL, NULL,
		   slt_par->time);
      if (err > 0)
	{
	  if (FD_ISSET(svr_sock, &(slt_par->fd_read)))
	    if (add_client(&vec, slt_par, svr_sock) == EXIT_FAILURE)
	      fprintf(stderr, "add client error");
	  fetch_instr(&vec, slt_par, game);
	}
      end_loop(&vec, slt_par, game, svr_sock);
    }
  close_client(&vec, slt_par);
  return (EXIT_SUCCESS);
}
//   Execute an instruction cycle
//   Fetch an instruction
//   Decode the instruction opcode
//   Execute the instruction
//
void instruction_cycle(CPU *cpu)
{
 // Get current instruction to execute and its location,
 // echo them out.
 //
    Address old_pc = cpu->pgm_counter;
    fetch_instr(cpu);
    printf("x%04hX: x%04hX  ", old_pc, cpu->instr_reg);
 
 // Execute instruction; set halt = 1 if execution is to stop
 // (TRAP HALT or internal error).
 //
    switch ((cpu->instr_reg)) // ** Note ** place "op(cpu->instr_reg))"
    {
        case  0:
            instr_BR(cpu);
            break;

 
        default:
            printf("Bad opcode: %d; quitting\n", (cpu->instr_reg)); // ** Note ** place "op(cpu->instr_reg))"
            cpu->running = 0;
    }
}
Пример #3
0
//--------------------------------------------------------------------
// int cycle_model::fetch_operand(operand* op)
//
//   returns the value of the operand
//
//--------------------------------------------------------------------
int cycle_model::fetch_operand(operand* op) {
  switch(op->type) {
  case o_acc: {
    return A;
    break;
  }
  case o_reg: {
    assert((op->val<8)&&(op->val>=0));
#ifdef DEBUG
    printf("read R%d=%d\n",op->val,R[op->val]); 
#endif
    return R[op->val];
    break;
  }
  case o_dir: {
    // fetch address
    my_stack->address += 1;
    int temp = fetch_instr(my_stack->address);
    assert((op->val<INT_SIZE)&&(op->val>=0));
    return int_mem[temp];
    break;
  }
  case o_ind: {
    assert((op->val==0)||(op->val==1));
    assert((R[op->val]<INT_SIZE)&&(R[op->val]>=0));
    return int_mem[R[op->val]];
    break;
  }
  case o_ext: {
    assert((op->val==1)||(op->val==0));
    int addr = R[op->val];
    assert((addr<MEM_SIZE)&&(addr>=0));
    
    int result = fetch_data(addr);

    return result;
    break;
  }
  case o_cst: {
    // fetch next byte
    my_stack->address += 1;
    int temp = fetch_instr(my_stack->address);
    return temp;
    break;
  }
  case o_lcst: {
    // fetch next 2 bytes

    my_stack->address += 1;
    int temp = fetch_instr(my_stack->address);

    my_stack->address += 1;
    assert(my_stack->address<=MEM_SIZE);
    temp = (temp<<8) +  fetch_instr(my_stack->address);

    return temp;
    break;
  }
  case o_add: {
    // fetch next byte
    my_stack->address += 1;
    int temp = ((op->val)<<8) + fetch_instr(my_stack->address);
    return temp;
    break;
  }	
  case o_ladd: {
    // fetch next 2 bytes
    my_stack->address += 1;
    int temp = fetch_instr(my_stack->address);

    my_stack->address += 1;
    temp = (temp<<8) + fetch_instr(my_stack->address);
    return temp;
    break;
  }
  case o_rel: {
    // fetch next byte
    my_stack->address += 1;
    int temp = fetch_instr(my_stack->address);
    if(temp<0x80)
      return temp;
    else
      return -(0x100-temp);
    break;
  }
  default: {
    return -1;
    break;
  }
  }
  return -1;
}
void instruction_cycle(CPU *cpu, int order)
{
 // Get current instruction to execute and its location,
 // echo them out.
 //
    Address old_pc = cpu->memory[cpu->pgm_counter+1]; // OLD: cpu->pgm_counter
    fetch_instr(cpu);
    
    int op_code = 0;
    u_reg = ((unsigned short int)(cpu->instr_reg));
	op_code = u_reg/4096;
    
    unsigned short movement1 = (old_pc << 4);
    unsigned short movement2 = (old_pc << 7);
    unsigned short movement3 = (old_pc << 12);
    unsigned short movement4 = (old_pc << 7);
    unsigned short movement5 = (old_pc << 13);
    
    Commands.opCode = (old_pc >> 12); // Finished
    
    Commands.intRest =  (old_pc << 8); // Finished
    Commands.trap = (Commands.intRest >> 8); // Finished
    
    Commands.NZP    =   (movement1 >> 13);
    Commands.offset =   (movement2 >> 7);
    Commands.last   =   (movement3 >> 12);
    Commands.Src1   =   (movement4 >> 6);
    Commands.Src2   =   (movement5 >> 13);
    
    
    /* Tests
     
    Output bit shifts
     
     
    printf("\nShowing whats in memory, dividing integers:\n\n");
    printf("First Hex: %hX\n", Commands.opCode);
    printf("Second Hex: %hX\n", Commands.intSecond);
    //printf("Remaining Hex: %hX\n", intRest);
    printf("NZP value: %hX\n", Commands.NZP);
    printf("offset value: %hX\n", Commands.offset);
    printf("Trap value (last 2 digits): %hX\n", Commands.trap);
    printf("Last value: %hX\n", Commands.last);
    */
     
    
 // Execute instruction; set halt = 1 if execution is to stop
 // (TRAP HALT or internal error).
 //
    switch ((Commands.opCode)) // ** Note ** place "op(cpu->instr_reg))"
    {
        case  0:
            if (Commands.NZP > 0){
                // Command loop that accounts for P and Z
                // Removed because of the lack of time
                
                /*if(Commands.NZP == 2){
                    printf("BRZ  3, CC = P, no go to\n");
                    //cpu->pgm_counter--;
                }
                else{ */
                order ++;
                printf("x%04X: x%04hX  ", order, old_pc);   // print location
                cpu->pgm_counter = cpu->pgm_counter + Commands.last;
                printf("BR   %d, CC = Z, go to x%04X+%d = x%04X\n", Commands.last, order, (signed short)Commands.last, (order + Commands.last));
                order = order + Commands.last;
            }
            else{
            instr_BR(cpu);
            }
            break;
            
        case 1:
            printf("x%04X: x%04hX  ", order, old_pc);
            instr_ADD(cpu);
            break;
            
        case 2:
            printf("x%04X: x%04hX  ", order, old_pc);
            instr_LD(cpu, order);
            break;
            
        case 3:
            printf("x%04X: x%04hX  ", order, old_pc);
            instr_ST(cpu, order);
            break;
            
        case 4:
            printf("x%04X: x%04hX  ", order, old_pc);
            instr_JSR(cpu);
            break;
            
        case 5:
            printf("x%04X: x%04hX  ", order, old_pc);
            instr_AND(cpu);
            break;
            
        case 6:
            printf("x%04X: x%04hX  ", order, old_pc);
            instr_LDR(cpu);
            break;
            
        case 7:
            printf("x%04X: x%04hX  ", order, old_pc);
            instr_STR(cpu);
            break;
            
        case 8:
            printf("x%04X: x%04hX  ", order, old_pc);
            instr_RTI(cpu);
            break;
            
        case 9:
            printf("x%04X: x%04hX  ", order, old_pc);
            instr_NOT(cpu);
            break;
            
        case 10:
            printf("x%04X: x%04hX  ", order, old_pc);
            instr_LDI(cpu);
            break;
            
        case 11:
            printf("x%04X: x%04hX  ", order, old_pc);
            instr_STI(cpu);
            break;
            
        case 12:
            printf("x%04X: x%04hX  ", order, old_pc);
            instr_JMP(cpu);
            break;
            
        case 13:
            printf("x%04X: x%04hX  ", order, old_pc);
            instr_err(cpu);
            break;
            
        case 14:
            printf("x%04X: x%04hX  ", order, old_pc);
            instr_LEA(cpu, order);
            break;
            
        case 15:
            printf("x%04X: x%04hX  ", order, old_pc);
            instr_TRAP(cpu);
            break;
            
            
        default:
            printf("Bad opcode: %d; quitting\n", (Commands.opCode)); // ** Note ** place "op(cpu->instr_reg))"
            cpu->running = 0;
    }
    old_pc++;
    
}