int flash_physical_is_erased(uint32_t offset, int size)
{
int dest_addr = offset;
uint32_t idx;
uint8_t temp;
/* Chip Select down. */
flash_cs_level(0);
/* Set read address */
flash_set_address(dest_addr);
/* Start fast read -1110 1001 - EXEC, WR, CMD, ADDR */
flash_execute_cmd(CMD_FAST_READ, MASK_CMD_ADR_WR);
/* Burst read transaction */
for (idx = 0; idx < size; idx++) {
/* 1101 0101 - EXEC, RD, NO CMD, NO ADDR, 4 bytes */
NPCX_UMA_CTS = MASK_RD_1BYTE;
/* Wait for UMA to complete */
while (IS_BIT_SET(NPCX_UMA_CTS, EXEC_DONE))
;
/* Get read transaction results */
temp = NPCX_UMA_DB0;
if (temp != 0xFF)
break;
}
/* Chip Select up */
flash_cs_level(1);
if (idx == size)
return 1;
else
return 0;
}
int flash_physical_read(int offset, int size, char *data)
{
int dest_addr = offset;
uint32_t idx;
/* Disable tri-state */
TRISTATE_FLASH(0);
/* Chip Select down. */
flash_cs_level(0);
/* Set read address */
flash_set_address(dest_addr);
/* Start fast read - 1110 1001 - EXEC, WR, CMD, ADDR */
flash_execute_cmd(CMD_FAST_READ, MASK_CMD_ADR_WR);
/* Burst read transaction */
for (idx = 0; idx < size; idx++) {
/* 1101 0101 - EXEC, RD, NO CMD, NO ADDR, 4 bytes */
NPCX_UMA_CTS = MASK_RD_1BYTE;
/* wait for UMA to complete */
while (IS_BIT_SET(NPCX_UMA_CTS, EXEC_DONE))
;
/* Get read transaction results*/
data[idx] = NPCX_UMA_DB0;
}
/* Chip Select up */
flash_cs_level(1);
/* Enable tri-state */
TRISTATE_FLASH(1);
return EC_SUCCESS;
}
int flash_physical_erase(int offset, int size)
{
int rv = EC_SUCCESS;
/* check protection */
if (all_protected)
return EC_ERROR_ACCESS_DENIED;
/* Lock physical flash operations */
flash_lock_mapped_storage(1);
/* Disable tri-state */
TRISTATE_FLASH(0);
/* Alignment has been checked in upper layer */
for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE,
offset += CONFIG_FLASH_ERASE_SIZE) {
/* check protection */
if (flash_check_prot_range(offset, CONFIG_FLASH_ERASE_SIZE)) {
rv = EC_ERROR_ACCESS_DENIED;
break;
}
/*
* Reload the watchdog timer, so that erasing many flash pages
* doesn't cause a watchdog reset. May not need this now that
* we're using msleep() below.
*/
watchdog_reload();
/* Enable write */
rv = flash_write_enable();
if (rv)
break;
/* Set erase address */
flash_set_address(offset);
/* Start erase */
flash_execute_cmd(CMD_SECTOR_ERASE, MASK_CMD_ADR);
/* Wait erase completed */
rv = flash_wait_ready(FLASH_ABORT_TIMEOUT);
if (rv)
break;
}
/* Enable tri-state */
TRISTATE_FLASH(1);
/* Unlock physical flash operations */
flash_lock_mapped_storage(0);
return rv;
}
void flash_get_mfr_dev_id(uint8_t *dest)
{
/* Disable tri-state */
TRISTATE_FLASH(0);
/* Read manufacturer and device ID. Send cmd=0x90 + 24-bit address=0 */
flash_set_address(0);
flash_execute_cmd(CMD_READ_MAN_DEV_ID,
MASK_CMD_RD_2BYTE | MASK(A_SIZE));
/* Enable tri-state */
TRISTATE_FLASH(1);
dest[0] = NPCX_UMA_DB0;
dest[1] = NPCX_UMA_DB1;
}
void flash_burst_write(unsigned int dest_addr, unsigned int bytes,
const char *data)
{
unsigned int i;
/* Chip Select down. */
flash_cs_level(0);
/* Set erase address */
flash_set_address(dest_addr);
/* Start write */
flash_execute_cmd(CMD_FLASH_PROGRAM, MASK_CMD_WR_ADR);
for (i = 0; i < bytes; i++) {
flash_execute_cmd(*data, MASK_CMD_WR_ONLY);
data++;
}
/* Chip Select up */
flash_cs_level(1);
}
int flash_physical_erase(int offset, int size)
{
/* check protection */
if (all_protected)
return EC_ERROR_ACCESS_DENIED;
/* Disable tri-state */
TRISTATE_FLASH(0);
/* Alignment has been checked in upper layer */
for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE,
offset += CONFIG_FLASH_ERASE_SIZE) {
/* Do nothing if already erased */
if (flash_is_erased(offset, CONFIG_FLASH_ERASE_SIZE))
continue;
/* check protection */
if (flash_check_prot_range(offset, CONFIG_FLASH_ERASE_SIZE))
return EC_ERROR_ACCESS_DENIED;
/*
* Reload the watchdog timer, so that erasing many flash pages
* doesn't cause a watchdog reset. May not need this now that
* we're using msleep() below.
*/
watchdog_reload();
/* Enable write */
flash_write_enable();
/* Set erase address */
flash_set_address(offset);
/* Start erase */
flash_execute_cmd(CMD_SECTOR_ERASE, MASK_CMD_ADR);
/* Wait erase completed */
flash_wait_ready();
}
/* Enable tri-state */
TRISTATE_FLASH(1);
return EC_SUCCESS;
}
static void flash_writel(u16 addr, u32 val)
{
preempt_disable();
isp_enter_mode(ISP_MODE_FLASH_WRITE);
flash_set_address(addr);
isp_send_bits(val, 32);
gpio_direction_output(GPIO_SDA, 1);
/* 6 clock cycles with different timings for the data to get written
* into flash */
isp_toggle_clk(0, 1, 3);
isp_toggle_clk(0, 1, 3);
isp_toggle_clk(0, 1, 6);
isp_toggle_clk(0, 1, 12);
isp_toggle_clk(0, 1, 3);
isp_toggle_clk(0, 1, 3);
isp_toggle_clk(1, 0, 1);
gpio_direction_output(GPIO_SDA, 0);
isp_exit_mode();
preempt_enable();
usleep_range(300, 400);
}
static u32 flash_readl(u16 addr)
{
int i;
u32 val;
preempt_disable();
isp_enter_mode(ISP_MODE_FLASH_READ);
flash_set_address(addr);
gpio_direction_output(GPIO_SCL, 0);
gpio_direction_output(GPIO_SDA, 0);
udelay(40);
/* data load cycle */
for (i = 0; i < 6; i++)
isp_toggle_clk(1, 0, 10);
val = isp_recv_bits(32);
isp_exit_mode();
preempt_enable();
return val;
}
int flash_physical_read_image_size(int offset, int size)
{
int dest_addr = offset;
uint8_t temp;
uint32_t idx;
uint32_t image_size = 0;
/* Disable tri-state */
TRISTATE_FLASH(0);
/* Chip Select down. */
flash_cs_level(0);
/* Set read address */
flash_set_address(dest_addr);
/* Start fast read - 1110 1001 - EXEC, WR, CMD, ADDR */
flash_execute_cmd(CMD_FAST_READ, MASK_CMD_ADR_WR);
/* Burst read transaction */
for (idx = 0; idx < size; idx++) {
/* 1101 0101 - EXEC, RD, NO CMD, NO ADDR, 4 bytes */
NPCX_UMA_CTS = MASK_RD_1BYTE;
/* wait for UMA to complete */
while (IS_BIT_SET(NPCX_UMA_CTS, EXEC_DONE))
;
/* Find eof of image */
temp = NPCX_UMA_DB0;
if (temp == 0xea)
image_size = idx;
}
/* Chip Select up */
flash_cs_level(1);
/* Enable tri-state */
TRISTATE_FLASH(1);
return image_size;
}
