void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm,
void *vfpst, uint32_t desc)
{
uintptr_t opr_sz = simd_oprsz(desc);
float32 *d = vd;
float32 *n = vn;
float32 *m = vm;
float_status *fpst = vfpst;
uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);
uint32_t neg_imag = neg_real ^ 1;
uintptr_t i;
/* Shift boolean to the sign bit so we can xor to negate. */
neg_real <<= 31;
neg_imag <<= 31;
for (i = 0; i < opr_sz / 4; i += 2) {
float32 e0 = n[H4(i)];
float32 e1 = m[H4(i + 1)] ^ neg_imag;
float32 e2 = n[H4(i + 1)];
float32 e3 = m[H4(i)] ^ neg_real;
d[H4(i)] = float32_add(e0, e1, fpst);
d[H4(i + 1)] = float32_add(e2, e3, fpst);
}
clear_tail(d, opr_sz, simd_maxsz(desc));
}
void helper_ftrv(CPUSH4State *env, uint32_t n)
{
int bank_matrix, bank_vector;
int i, j;
float32 r[4];
float32 p;
bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
set_float_exception_flags(0, &env->fp_status);
for (i = 0 ; i < 4 ; i++) {
r[i] = float32_zero;
for (j = 0 ; j < 4 ; j++) {
p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
env->fregs[bank_vector + j],
&env->fp_status);
r[i] = float32_add(r[i], p, &env->fp_status);
}
}
update_fpscr(env, GETPC());
for (i = 0 ; i < 4 ; i++) {
env->fregs[bank_vector + i] = r[i];
}
}
float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
{
set_float_exception_flags(0, &env->fp_status);
t0 = float32_add(t0, t1, &env->fp_status);
update_fpscr(env, GETPC());
return t0;
}
/* 32-bit FP multiply and add RR */
void HELPER(maebr)(CPUS390XState *env, uint32_t f1, uint32_t f3, uint32_t f2)
{
env->fregs[f1].l.upper = float32_add(env->fregs[f1].l.upper,
float32_mul(env->fregs[f2].l.upper,
env->fregs[f3].l.upper,
&env->fpu_status),
&env->fpu_status);
}
uint32_t helper_fadd_FT(uint32_t t0, uint32_t t1)
{
CPU_FloatU f0, f1;
f0.l = t0;
f1.l = t1;
f0.f = float32_add(f0.f, f1.f, &env->fp_status);
return f0.l;
}
float32 helper_fmac_FT(float32 t0, float32 t1, float32 t2)
{
set_float_exception_flags(0, &env->fp_status);
t0 = float32_mul(t0, t1, &env->fp_status);
t0 = float32_add(t0, t2, &env->fp_status);
update_fpscr(GETPC());
return t0;
}
/* 32-bit FP addition RM */
void HELPER(aeb)(CPUS390XState *env, uint32_t f1, uint32_t val)
{
float32 v1 = env->fregs[f1].l.upper;
CPU_FloatU v2;
v2.l = val;
HELPER_LOG("%s: adding 0x%d from f%d and 0x%d\n", __func__,
v1, f1, v2.f);
env->fregs[f1].l.upper = float32_add(v1, v2.f, &env->fpu_status);
}
/* 32-bit FP addition RR */
uint32_t HELPER(aebr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
env->fregs[f1].l.upper = float32_add(env->fregs[f1].l.upper,
env->fregs[f2].l.upper,
&env->fpu_status);
HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __func__,
env->fregs[f2].l.upper, env->fregs[f1].l.upper, f1);
return set_cc_nz_f32(env->fregs[f1].l.upper);
}
uint32_t helper_fmac_FT(uint32_t t0, uint32_t t1, uint32_t t2)
{
CPU_FloatU f0, f1, f2;
f0.l = t0;
f1.l = t1;
f2.l = t2;
f0.f = float32_mul(f0.f, f1.f, &env->fp_status);
f0.f = float32_add(f0.f, f2.f, &env->fp_status);
return f0.l;
}
uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
{
CPU_FloatU fd, fa, fb;
int flags;
set_float_exception_flags(0, &env->fp_status);
fa.l = a;
fb.l = b;
fd.f = float32_add(fa.f, fb.f, &env->fp_status);
flags = get_float_exception_flags(&env->fp_status);
update_fpu_flags(env, flags);
return fd.l;
}
void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
{
int bank, i;
float32 r, p;
bank = (env->sr & FPSCR_FR) ? 16 : 0;
r = float32_zero;
set_float_exception_flags(0, &env->fp_status);
for (i = 0 ; i < 4 ; i++) {
p = float32_mul(env->fregs[bank + m + i],
env->fregs[bank + n + i],
&env->fp_status);
r = float32_add(r, p, &env->fp_status);
}
update_fpscr(env, GETPC());
env->fregs[bank + n + 3] = r;
}
int arop(int count, int op) {
float32 f1, f2, f3, f4;
int i;
int fp;
char *mode;
int add=0;
int sub=0;
int mul=0;
int div=0;
int oper;
int err;
int err_count=0;
if(!quiet) printf("\nGenerating %0d Arithmetic test vectors ...\n",count);
if(append) mode = "a";
else mode = "w";
if(ofile==0) ofile = "ar.hex";
fp = fopen(ofile,mode);
if(fp == 0) {
printf("ERROR: Could not create file '%s'.\n",ofile);
return(-1);
}
if(!quiet) {
if(op & 0x1) printf("Add OP\n");
if(op & 0x2) printf("Sub OP\n");
if(op & 0x4) printf("Mul OP\n");
if(op & 0x8) printf("Div OP\n");
}
if(op & 0x1) add=1;
if(op & 0x2) sub=1;
if(op & 0x4) mul=1;
if(op & 0x8) div=1;
f1 = get_pat(0); // Initialize pattern generator ...
for(i=0;i<count;i++) {
err = 0;
if(pat>0) {
f1 = get_pat(1);
f2 = get_pat(2);
} else {
f1 = get_fp();
f2 = get_fp();
}
if(rall) float_rounding_mode = (rand() % 4);
oper = -1;
while(oper == -1) {
float_exception_flags = 0; // Reset Exceptions
if( (rand() % 4)==3 & div) {
oper = 8;
f3 = float32_div( f1, f2);
float_exception_flags = 0; // Reset Exceptions
f3 = float32_div( f1, f2);
//*( (float *) &f4 ) = *( (float *) &f1 ) / *( (float *) &f2 );
//if( f4 != f3) {
// err = 1;
// printf("FP Div Error: %x - %x: System: %x Lib: %x\n",f1, f2, f4, f3);
// }
}
if( (rand() % 4)==2 & mul) {
oper = 4;
f3 = float32_mul( f1, f2);
float_exception_flags = 0; // Reset Exceptions
f3 = float32_mul( f1, f2);
//*( (float *) &f4 ) = *( (float *) &f1 ) * *( (float *) &f2 );
//if( f4 != f3) {
// err = 1;
// printf("FP Mul Error: %x - %x: System: %x Lib: %x\n",f1, f2, f4, f3);
// }
}
if( (rand() % 4)==1 & sub) {
oper = 2;
f3 = float32_sub( f1, f2);
float_exception_flags = 0; // Reset Exceptions
f3 = float32_sub( f1, f2);
//*( (float *) &f4 ) = *( (float *) &f1 ) - *( (float *) &f2 );
//if( f4 != f3) {
// err = 1;
// printf("FP Sub Error: %x - %x: System: %x Lib: %x\n",f1, f2, f4, f3);
// }
}
if( (rand() % 4)==0 & add) {
oper = 1;
f3 = float32_add( f1, f2);
float_exception_flags = 0; // Reset Exceptions
f3 = float32_add( f1, f2);
//*( (float *) &f4 ) = *( (float *) &f1 ) + *( (float *) &f2 );
//if( f4 != f3) {
// err = 1;
// printf("FP Add Error: %x - %x: System: %x Lib: %x\n",f1, f2, f4, f3);
// }
}
}
if(err) err_count++;
if(!err) {
//if(float_exception_flags != 0)
// printf("Exceptions: %x\n",float_exception_flags);
if(verb) printf("rmode: %01x, except: %02x, oper: %01x opa: %08x, opb: %08x res: %08x\n", float_rounding_mode, float_exception_flags, oper, f1, f2, f3);
fprintf(fp,"%01x%02x%01x%08x%08x%08x\n", float_rounding_mode, float_exception_flags, oper, f1, f2, f3);
}
else {
printf("\t Vecor mismatch between library and system calculations. This Vector\n");
printf("\t will not be placed in to vector file ...\n");
}
}
close(fp);
if(!quiet) {
printf("Found %d errors\n",err_count);
printf("Wrote %d vectors from total %d specified.\n", (count-err_count), count);
printf("\n ... f2i done.\n");
}
return(0);
}
float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b)
{
return float32_add(a, b, &env->fp_status);
}
float32 __addsf3(float32 A, float32 B)
{
return float32_add(A, B);
}
unsigned int SingleCPDO(const unsigned int opcode)
{
FPA11 *fpa11 = GET_FPA11();
float32 rFm, rFn = float32_zero;
unsigned int Fd, Fm, Fn, nRc = 1;
Fm = getFm(opcode);
if (CONSTANT_FM(opcode))
{
rFm = getSingleConstant(Fm);
}
else
{
switch (fpa11->fType[Fm])
{
case typeSingle:
rFm = fpa11->fpreg[Fm].fSingle;
break;
default: return 0;
}
}
if (!MONADIC_INSTRUCTION(opcode))
{
Fn = getFn(opcode);
switch (fpa11->fType[Fn])
{
case typeSingle:
rFn = fpa11->fpreg[Fn].fSingle;
break;
default: return 0;
}
}
Fd = getFd(opcode);
switch (opcode & MASK_ARITHMETIC_OPCODE)
{
/* dyadic opcodes */
case ADF_CODE:
fpa11->fpreg[Fd].fSingle = float32_add(rFn,rFm, &fpa11->fp_status);
break;
case MUF_CODE:
case FML_CODE:
fpa11->fpreg[Fd].fSingle = float32_mul(rFn,rFm, &fpa11->fp_status);
break;
case SUF_CODE:
fpa11->fpreg[Fd].fSingle = float32_sub(rFn,rFm, &fpa11->fp_status);
break;
case RSF_CODE:
fpa11->fpreg[Fd].fSingle = float32_sub(rFm,rFn, &fpa11->fp_status);
break;
case DVF_CODE:
case FDV_CODE:
fpa11->fpreg[Fd].fSingle = float32_div(rFn,rFm, &fpa11->fp_status);
break;
case RDF_CODE:
case FRD_CODE:
fpa11->fpreg[Fd].fSingle = float32_div(rFm,rFn, &fpa11->fp_status);
break;
#if 0
case POW_CODE:
fpa11->fpreg[Fd].fSingle = float32_pow(rFn,rFm);
break;
case RPW_CODE:
fpa11->fpreg[Fd].fSingle = float32_pow(rFm,rFn);
break;
#endif
case RMF_CODE:
fpa11->fpreg[Fd].fSingle = float32_rem(rFn,rFm, &fpa11->fp_status);
break;
#if 0
case POL_CODE:
fpa11->fpreg[Fd].fSingle = float32_pol(rFn,rFm);
break;
#endif
/* monadic opcodes */
case MVF_CODE:
fpa11->fpreg[Fd].fSingle = rFm;
break;
case MNF_CODE:
fpa11->fpreg[Fd].fSingle = float32_chs(rFm);
break;
case ABS_CODE:
fpa11->fpreg[Fd].fSingle = float32_abs(rFm);
break;
case RND_CODE:
case URD_CODE:
fpa11->fpreg[Fd].fSingle = float32_round_to_int(rFm, &fpa11->fp_status);
break;
case SQT_CODE:
fpa11->fpreg[Fd].fSingle = float32_sqrt(rFm, &fpa11->fp_status);
break;
#if 0
case LOG_CODE:
fpa11->fpreg[Fd].fSingle = float32_log(rFm);
break;
case LGN_CODE:
fpa11->fpreg[Fd].fSingle = float32_ln(rFm);
break;
case EXP_CODE:
fpa11->fpreg[Fd].fSingle = float32_exp(rFm);
break;
case SIN_CODE:
fpa11->fpreg[Fd].fSingle = float32_sin(rFm);
break;
case COS_CODE:
fpa11->fpreg[Fd].fSingle = float32_cos(rFm);
break;
case TAN_CODE:
fpa11->fpreg[Fd].fSingle = float32_tan(rFm);
break;
case ASN_CODE:
fpa11->fpreg[Fd].fSingle = float32_arcsin(rFm);
break;
case ACS_CODE:
fpa11->fpreg[Fd].fSingle = float32_arccos(rFm);
break;
case ATN_CODE:
fpa11->fpreg[Fd].fSingle = float32_arctan(rFm);
break;
#endif
case NRM_CODE:
break;
default:
{
nRc = 0;
}
}
if (0 != nRc) fpa11->fType[Fd] = typeSingle;
return nRc;
}
float32 __aeabi_fadd(float32 a, float32 b)
{
return float32_add(a, b);
}
