int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET struct fsl_pq_mdio_info dtsec_mdio_info; unsigned int i; printf("Initializing Fman\n"); /* Register the real 1G MDIO bus */ dtsec_mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; fsl_pq_mdio_init(bis, &dtsec_mdio_info); fm_info_set_phy_address(FIRST_PORT, FIRST_PORT_ADDR); fm_info_set_mdio(FIRST_PORT, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); fm_info_set_phy_address(SECOND_PORT, SECOND_PORT_ADDR); fm_info_set_mdio(SECOND_PORT, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); /* Never disable DTSEC1 - it controls MDIO */ for (i = FM1_DTSEC2; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { if (!IS_VALID_PORT(i)) fm_disable_port(i); } #ifdef CONFIG_PPC_P5040 for (i = FM2_DTSEC2; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { if (!IS_VALID_PORT(i)) fm_disable_port(i); } #endif cpu_eth_init(bis); cyrus_phy_tuning(FIRST_PORT_ADDR); cyrus_phy_tuning(SECOND_PORT_ADDR); #endif return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #if defined(CONFIG_FMAN_ENET) int i, idx, lane, slot, interface; struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 srds_s1; srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; initialize_lane_to_slot(); /* Initialize the mdio_mux array so we can recognize empty elements */ for (i = 0; i < NUM_FM_PORTS; i++) mdio_mux[i] = EMI_NONE; dtsec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the 1G MDIO bus */ fm_memac_mdio_init(bis, &dtsec_mdio_info); tgec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; /* Register the 10G MDIO bus */ fm_memac_mdio_init(bis, &tgec_mdio_info); /* Register the muxing front-ends to the MDIO buses */ t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); t1024qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); /* Set the two on-board RGMII PHY address */ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); switch (srds_s1) { case 0xd5: case 0xd6: /* QSGMII in Slot2 */ fm_info_set_phy_address(FM1_DTSEC1, 0x8); fm_info_set_phy_address(FM1_DTSEC2, 0x9); fm_info_set_phy_address(FM1_DTSEC3, 0xa); fm_info_set_phy_address(FM1_DTSEC4, 0xb); break; case 0x95: case 0x99: /* * XFI does not need a PHY to work, but to avoid U-boot use * default PHY address which is zero to a MAC when it found * a MAC has no PHY address, we give a PHY address to XFI * MAC, and should not use a real XAUI PHY address, since * MDIO can access it successfully, and then MDIO thinks the * XAUI card is used for the XFI MAC, which will cause error. */ fm_info_set_phy_address(FM1_10GEC1, 4); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); break; case 0x6f: /* SGMII in Slot3, Slot4, Slot5 */ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4); fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); break; case 0x7f: fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4); fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3); break; case 0x47: fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); break; case 0x77: fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3); break; case 0x5a: fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); break; case 0x6a: fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); break; case 0x5b: fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); break; case 0x6b: fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); break; default: break; } for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { idx = i - FM1_DTSEC1; interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_SGMII_2500: case PHY_INTERFACE_MODE_QSGMII: if (interface == PHY_INTERFACE_MODE_SGMII) { lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1 + idx); } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) { lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_2500_FM1_DTSEC1 + idx); } else { lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_FM1_A); } if (lane < 0) break; slot = lane_to_slot[lane]; debug("FM1@DTSEC%u expects SGMII in slot %u\n", idx + 1, slot); if (QIXIS_READ(present2) & (1 << (slot - 1))) fm_disable_port(i); switch (slot) { case 2: mdio_mux[i] = EMI1_SLOT2; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 3: mdio_mux[i] = EMI1_SLOT3; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 4: mdio_mux[i] = EMI1_SLOT4; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 5: mdio_mux[i] = EMI1_SLOT5; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; } break; case PHY_INTERFACE_MODE_RGMII: if (i == FM1_DTSEC3) mdio_mux[i] = EMI1_RGMII2; else if (i == FM1_DTSEC4) mdio_mux[i] = EMI1_RGMII1; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; default: break; } } for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { idx = i - FM1_10GEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: lane = serdes_get_first_lane(FSL_SRDS_1, XFI_FM1_MAC1 + idx); if (lane < 0) break; mdio_mux[i] = EMI2; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; default: break; } } cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET int i, idx, lane, slot, interface; struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 srds_s1; srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; /* Initialize the mdio_mux array so we can recognize empty elements */ for (i = 0; i < NUM_FM_PORTS; i++) mdio_mux[i] = EMI_NONE; dtsec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the 1G MDIO bus */ fm_memac_mdio_init(bis, &dtsec_mdio_info); tgec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; /* Register the 10G MDIO bus */ fm_memac_mdio_init(bis, &tgec_mdio_info); /* Register the muxing front-ends to the MDIO buses */ ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); /* Set the two on-board RGMII PHY address */ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); switch (srds_s1) { case 0x2555: /* 2.5G SGMII on lane A, MAC 9 */ fm_info_set_phy_address(FM1_DTSEC9, 9); break; case 0x4555: case 0x4558: /* QSGMII on lane A, MAC 1/2/5/6 */ fm_info_set_phy_address(FM1_DTSEC1, QSGMII_CARD_PORT1_PHY_ADDR_S1); fm_info_set_phy_address(FM1_DTSEC2, QSGMII_CARD_PORT2_PHY_ADDR_S1); fm_info_set_phy_address(FM1_DTSEC5, QSGMII_CARD_PORT3_PHY_ADDR_S1); fm_info_set_phy_address(FM1_DTSEC6, QSGMII_CARD_PORT4_PHY_ADDR_S1); break; case 0x1355: /* SGMII on lane B, MAC 2*/ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); break; case 0x2355: /* 2.5G SGMII on lane A, MAC 9 */ fm_info_set_phy_address(FM1_DTSEC9, 9); /* SGMII on lane B, MAC 2*/ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); break; case 0x3335: /* SGMII on lane C, MAC 5 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); case 0x3355: case 0x3358: /* SGMII on lane B, MAC 2 */ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); case 0x3555: case 0x3558: /* SGMII on lane A, MAC 9 */ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); break; case 0x1455: /* QSGMII on lane B, MAC 1/2/5/6 */ fm_info_set_phy_address(FM1_DTSEC1, QSGMII_CARD_PORT1_PHY_ADDR_S2); fm_info_set_phy_address(FM1_DTSEC2, QSGMII_CARD_PORT2_PHY_ADDR_S2); fm_info_set_phy_address(FM1_DTSEC5, QSGMII_CARD_PORT3_PHY_ADDR_S2); fm_info_set_phy_address(FM1_DTSEC6, QSGMII_CARD_PORT4_PHY_ADDR_S2); break; case 0x2455: /* 2.5G SGMII on lane A, MAC 9 */ fm_info_set_phy_address(FM1_DTSEC9, 9); /* QSGMII on lane B, MAC 1/2/5/6 */ fm_info_set_phy_address(FM1_DTSEC1, QSGMII_CARD_PORT1_PHY_ADDR_S2); fm_info_set_phy_address(FM1_DTSEC2, QSGMII_CARD_PORT2_PHY_ADDR_S2); fm_info_set_phy_address(FM1_DTSEC5, QSGMII_CARD_PORT3_PHY_ADDR_S2); fm_info_set_phy_address(FM1_DTSEC6, QSGMII_CARD_PORT4_PHY_ADDR_S2); break; case 0x2255: /* 2.5G SGMII on lane A, MAC 9 */ fm_info_set_phy_address(FM1_DTSEC9, 9); /* 2.5G SGMII on lane B, MAC 2 */ fm_info_set_phy_address(FM1_DTSEC2, 2); break; case 0x3333: /* SGMII on lane A/B/C/D, MAC 9/2/5/6 */ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT1_PHY_ADDR); break; default: printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n", srds_s1); break; } for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { idx = i - FM1_DTSEC1; interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_SGMII_2500: case PHY_INTERFACE_MODE_QSGMII: if (interface == PHY_INTERFACE_MODE_SGMII) { lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1 + idx); } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) { lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_2500_FM1_DTSEC1 + idx); } else { lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_FM1_A); } if (lane < 0) break; slot = lane_to_slot[lane]; debug("FM1@DTSEC%u expects SGMII in slot %u\n", idx + 1, slot); if (QIXIS_READ(present2) & (1 << (slot - 1))) fm_disable_port(i); switch (slot) { case 1: mdio_mux[i] = EMI1_SLOT1; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 2: mdio_mux[i] = EMI1_SLOT2; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 3: mdio_mux[i] = EMI1_SLOT3; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 4: mdio_mux[i] = EMI1_SLOT4; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; default: break; } break; case PHY_INTERFACE_MODE_RGMII: if (i == FM1_DTSEC3) mdio_mux[i] = EMI1_RGMII1; else if (i == FM1_DTSEC4) mdio_mux[i] = EMI1_RGMII2; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; default: break; } } cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET int i, idx, lane, slot, interface; struct memac_mdio_info dtsec_mdio_info; struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 srds_s1, srds_s2; u8 brdcfg12; srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; srds_s2 = in_be32(&gur->rcwsr[4]) & FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT; /* Initialize the mdio_mux array so we can recognize empty elements */ for (i = 0; i < NUM_FM_PORTS; i++) mdio_mux[i] = EMI_NONE; dtsec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the 1G MDIO bus */ fm_memac_mdio_init(bis, &dtsec_mdio_info); /* Register the muxing front-ends to the MDIO buses */ ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); /* Set the two on-board RGMII PHY address */ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); switch (srds_s1) { case 0x3333: /* SGMII on slot 1, MAC 9 */ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); case 0x1333: case 0x2333: /* SGMII on slot 1, MAC 10 */ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); case 0x1133: case 0x2233: /* SGMII on slot 1, MAC 5/6 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); break; case 0x1040: case 0x2040: /* QSGMII on lane B, MAC 6/5/10/1 */ fm_info_set_phy_address(FM1_DTSEC6, QSGMII_CARD_PORT1_PHY_ADDR_S2); fm_info_set_phy_address(FM1_DTSEC5, QSGMII_CARD_PORT2_PHY_ADDR_S2); fm_info_set_phy_address(FM1_DTSEC10, QSGMII_CARD_PORT3_PHY_ADDR_S2); fm_info_set_phy_address(FM1_DTSEC1, QSGMII_CARD_PORT4_PHY_ADDR_S2); break; case 0x3363: /* SGMII on slot 1, MAC 9/10 */ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); case 0x1163: case 0x2263: case 0x2223: /* SGMII on slot 1, MAC 6 */ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); break; default: printf("Invalid SerDes protocol 0x%x for LS1046AQDS\n", srds_s1); break; } if (srds_s2 == 0x5a59 || srds_s2 == 0x5a06) /* SGMII on slot 4, MAC 2 */ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { idx = i - FM1_DTSEC1; interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: if (interface == PHY_INTERFACE_MODE_SGMII) { if (i == FM1_DTSEC5) { /* route lane 2 to slot1 so to have * one sgmii riser card supports * MAC5 and MAC6. */ brdcfg12 = QIXIS_READ(brdcfg[12]); QIXIS_WRITE(brdcfg[12], brdcfg12 | 0x80); } lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1 + idx); } else { /* clear the bit 7 to route lane B on slot2. */ brdcfg12 = QIXIS_READ(brdcfg[12]); QIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f); lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_FM1_A); lane_to_slot[lane] = 2; } if (i == FM1_DTSEC2) lane = 5; if (lane < 0) break; slot = lane_to_slot[lane]; debug("FM1@DTSEC%u expects SGMII in slot %u\n", idx + 1, slot); if (QIXIS_READ(present2) & (1 << (slot - 1))) fm_disable_port(i); switch (slot) { case 1: mdio_mux[i] = EMI1_SLOT1; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 2: mdio_mux[i] = EMI1_SLOT2; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 4: mdio_mux[i] = EMI1_SLOT4; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; default: break; } break; case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_TXID: if (i == FM1_DTSEC3) mdio_mux[i] = EMI1_RGMII1; else if (i == FM1_DTSEC4) mdio_mux[i] = EMI1_RGMII2; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; default: break; } } cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #if defined(CONFIG_FMAN_ENET) int i, idx, lane, slot, interface; struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 rcwsr13 = in_be32(&gur->rcwsr[13]); u32 srds_s1; srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; initialize_lane_to_slot(); /* Initialize the mdio_mux array so we can recognize empty elements */ for (i = 0; i < NUM_FM_PORTS; i++) mdio_mux[i] = EMI_NONE; dtsec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the 1G MDIO bus */ fm_memac_mdio_init(bis, &dtsec_mdio_info); tgec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; /* Register the 10G MDIO bus */ fm_memac_mdio_init(bis, &tgec_mdio_info); /* Register the muxing front-ends to the MDIO buses */ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); #if defined(CONFIG_T2080QDS) t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); #endif t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); #if defined(CONFIG_T2081QDS) t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6); t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); #endif t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); /* Set the two on-board RGMII PHY address */ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII) fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); else fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR); switch (srds_s1) { case 0x1b: case 0x1c: case 0x95: case 0xa2: case 0x94: /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); break; case 0x50: case 0x51: case 0x5e: case 0x5f: case 0x64: case 0x65: /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); break; case 0x66: case 0x67: /* * XFI does not need a PHY to work, but to avoid U-boot use * default PHY address which is zero to a MAC when it found * a MAC has no PHY address, we give a PHY address to XFI * MAC, and should not use a real XAUI PHY address, since * MDIO can access it successfully, and then MDIO thinks * the XAUI card is used for the XFI MAC, which will cause * error. */ fm_info_set_phy_address(FM1_10GEC1, 4); fm_info_set_phy_address(FM1_10GEC2, 5); fm_info_set_phy_address(FM1_10GEC3, 6); fm_info_set_phy_address(FM1_10GEC4, 7); break; case 0x6a: case 0x6b: fm_info_set_phy_address(FM1_10GEC1, 4); fm_info_set_phy_address(FM1_10GEC2, 5); fm_info_set_phy_address(FM1_10GEC3, 6); fm_info_set_phy_address(FM1_10GEC4, 7); /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); break; case 0x6c: case 0x6d: fm_info_set_phy_address(FM1_10GEC1, 4); fm_info_set_phy_address(FM1_10GEC2, 5); /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); break; case 0x70: case 0x71: /* SGMII in Slot3 */ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); /* SGMII in Slot2 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); break; case 0xa6: case 0x8e: case 0x8f: case 0x82: case 0x83: /* SGMII in Slot3 */ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); /* SGMII in Slot2 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); break; case 0xa4: case 0x96: case 0x8a: /* SGMII in Slot3 */ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); break; #if defined(CONFIG_T2080QDS) case 0xd9: case 0xd3: case 0xcb: /* SGMII in Slot3 */ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); /* SGMII in Slot2 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); break; #elif defined(CONFIG_T2081QDS) case 0xca: case 0xcb: /* SGMII in Slot3 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); /* SGMII in Slot5 */ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); /* SGMII in Slot6 */ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); /* SGMII in Slot7 */ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); break; #endif case 0xf2: /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); break; default: break; } for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { idx = i - FM1_DTSEC1; interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_SGMII: lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1 + idx); if (lane < 0) break; slot = lane_to_slot[lane]; debug("FM1@DTSEC%u expects SGMII in slot %u\n", idx + 1, slot); if (QIXIS_READ(present2) & (1 << (slot - 1))) fm_disable_port(i); switch (slot) { case 1: mdio_mux[i] = EMI1_SLOT1; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 2: mdio_mux[i] = EMI1_SLOT2; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 3: mdio_mux[i] = EMI1_SLOT3; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; #if defined(CONFIG_T2081QDS) case 5: mdio_mux[i] = EMI1_SLOT5; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 6: mdio_mux[i] = EMI1_SLOT6; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 7: mdio_mux[i] = EMI1_SLOT7; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; #endif } break; case PHY_INTERFACE_MODE_RGMII: if (i == FM1_DTSEC3) mdio_mux[i] = EMI1_RGMII1; else if (i == FM1_DTSEC4 || FM1_DTSEC10) mdio_mux[i] = EMI1_RGMII2; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; default: break; } } for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { idx = i - FM1_10GEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: if (srds_s1 == 0x51) { lane = serdes_get_first_lane(FSL_SRDS_1, XAUI_FM1_MAC9 + idx); } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) { lane = serdes_get_first_lane(FSL_SRDS_1, HIGIG_FM1_MAC9 + idx); } else { if (i == FM1_10GEC1 || i == FM1_10GEC2) lane = serdes_get_first_lane(FSL_SRDS_1, XFI_FM1_MAC9 + idx); else lane = serdes_get_first_lane(FSL_SRDS_1, XFI_FM1_MAC1 + idx); } if (lane < 0) break; mdio_mux[i] = EMI2; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) || (srds_s1 == 0x6a) || (srds_s1 == 0x70) || (srds_s1 == 0x6c) || (srds_s1 == 0x6d) || (srds_s1 == 0x71)) { /* As XFI is in cage intead of a slot, so * ensure doesn't disable the corresponding port */ break; } slot = lane_to_slot[lane]; if (QIXIS_READ(present2) & (1 << (slot - 1))) fm_disable_port(i); break; default: break; } } cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #if defined(CONFIG_FMAN_ENET) int i, idx, lane, slot, interface; struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 srds_prtcl_s1, srds_prtcl_s2; srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; /* Initialize the mdio_mux array so we can recognize empty elements */ for (i = 0; i < NUM_FM_PORTS; i++) mdio_mux[i] = EMI_NONE; dtsec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the 1G MDIO bus */ fm_memac_mdio_init(bis, &dtsec_mdio_info); tgec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR; tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; /* Register the 10G MDIO bus */ fm_memac_mdio_init(bis, &tgec_mdio_info); /* Register the muxing front-ends to the MDIO buses */ t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII); t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); initialize_qsgmiiphy_fix(); switch (srds_prtcl_s1) { case 1: case 2: case 4: /* XAUI/HiGig in Slot1 and Slot2 */ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); break; case 28: case 36: /* SGMII in Slot1 and Slot2 */ fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]); fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]); fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]); fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { fm_info_set_phy_address(FM1_DTSEC9, slot_qsgmii_phyaddr[1][3]); fm_info_set_phy_address(FM1_DTSEC10, slot_qsgmii_phyaddr[1][2]); } break; case 38: fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]); fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]); fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]); fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { fm_info_set_phy_address(FM1_DTSEC9, slot_qsgmii_phyaddr[1][2]); fm_info_set_phy_address(FM1_DTSEC10, slot_qsgmii_phyaddr[1][3]); } break; case 40: case 46: case 48: fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { fm_info_set_phy_address(FM1_DTSEC10, slot_qsgmii_phyaddr[1][2]); fm_info_set_phy_address(FM1_DTSEC9, slot_qsgmii_phyaddr[1][3]); } fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]); fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]); fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]); break; default: puts("Invalid SerDes1 protocol for T4240QDS\n"); break; } for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { idx = i - FM1_DTSEC1; interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: if (interface == PHY_INTERFACE_MODE_QSGMII) { if (idx <= 3) lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_FM1_A); else lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_FM1_B); if (lane < 0) break; slot = lane_to_slot_fsm1[lane]; debug("FM1@DTSEC%u expects QSGMII in slot %u\n", idx + 1, slot); } else { lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1 + idx); if (lane < 0) break; slot = lane_to_slot_fsm1[lane]; debug("FM1@DTSEC%u expects SGMII in slot %u\n", idx + 1, slot); } if (QIXIS_READ(present2) & (1 << (slot - 1))) fm_disable_port(i); switch (slot) { case 1: mdio_mux[i] = EMI1_SLOT1; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; case 2: mdio_mux[i] = EMI1_SLOT2; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; }; break; case PHY_INTERFACE_MODE_RGMII: /* FM1 DTSEC5 routes to RGMII with EC2 */ debug("FM1@DTSEC%u is RGMII at address %u\n", idx + 1, 2); if (i == FM1_DTSEC5) fm_info_set_phy_address(i, 2); mdio_mux[i] = EMI1_RGMII; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; default: break; } } for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { idx = i - FM1_10GEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: lane = serdes_get_first_lane(FSL_SRDS_1, XAUI_FM1_MAC9 + idx); if (lane < 0) break; slot = lane_to_slot_fsm1[lane]; if (QIXIS_READ(present2) & (1 << (slot - 1))) fm_disable_port(i); mdio_mux[i] = EMI2; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; default: break; } } #if (CONFIG_SYS_NUM_FMAN == 2) switch (srds_prtcl_s2) { case 1: case 2: case 4: /* XAUI/HiGig in Slot3 and Slot4 */ fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR); break; case 7: case 13: case 14: case 16: case 22: case 23: case 25: case 26: /* XAUI/HiGig in Slot3, SGMII in Slot4 */ fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); break; case 28: case 36: /* SGMII in Slot3 and Slot4 */ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]); fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]); fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]); fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]); break; case 38: /* QSGMII in Slot3 and Slot4 */ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]); fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]); fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]); fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]); break; case 40: case 46: case 48: /* SGMII in Slot3 */ fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]); fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]); fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]); fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]); /* QSGMII in Slot4 */ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); break; case 50: case 52: case 54: fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); break; case 56: case 57: /* XFI in Slot3, SGMII in Slot4 */ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); break; default: puts("Invalid SerDes2 protocol for T4240QDS\n"); break; } for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { idx = i - FM2_DTSEC1; interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: if (interface == PHY_INTERFACE_MODE_QSGMII) { if (idx <= 3) lane = serdes_get_first_lane(FSL_SRDS_2, QSGMII_FM2_A); else lane = serdes_get_first_lane(FSL_SRDS_2, QSGMII_FM2_B); if (lane < 0) break; slot = lane_to_slot_fsm2[lane]; debug("FM2@DTSEC%u expects QSGMII in slot %u\n", idx + 1, slot); } else { lane = serdes_get_first_lane(FSL_SRDS_2, SGMII_FM2_DTSEC1 + idx); if (lane < 0) break; slot = lane_to_slot_fsm2[lane]; debug("FM2@DTSEC%u expects SGMII in slot %u\n", idx + 1, slot); } if (QIXIS_READ(present2) & (1 << (slot - 1))) fm_disable_port(i); switch (slot) { case 3: mdio_mux[i] = EMI1_SLOT3; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; case 4: mdio_mux[i] = EMI1_SLOT4; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; }; break; case PHY_INTERFACE_MODE_RGMII: /* * If DTSEC5 is RGMII, then it's routed via via EC1 to * the first on-board RGMII port. If DTSEC6 is RGMII, * then it's routed via via EC2 to the second on-board * RGMII port. */ debug("FM2@DTSEC%u is RGMII at address %u\n", idx + 1, i == FM2_DTSEC5 ? 1 : 2); fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2); mdio_mux[i] = EMI1_RGMII; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; default: break; } } for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { idx = i - FM2_10GEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: lane = serdes_get_first_lane(FSL_SRDS_2, XAUI_FM2_MAC9 + idx); if (lane < 0) break; slot = lane_to_slot_fsm2[lane]; if (QIXIS_READ(present2) & (1 << (slot - 1))) fm_disable_port(i); mdio_mux[i] = EMI2; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; default: break; } } #endif /* CONFIG_SYS_NUM_FMAN */ cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #if defined(CONFIG_FMAN_ENET) int i, interface; struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; struct mii_dev *dev; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 srds_prtcl_s1, srds_prtcl_s2; srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; dtsec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the 1G MDIO bus */ fm_memac_mdio_init(bis, &dtsec_mdio_info); tgec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR; tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; /* Register the 10G MDIO bus */ fm_memac_mdio_init(bis, &tgec_mdio_info); if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) { /* SGMII */ fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1); fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2); fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3); fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4); } else { puts("Invalid SerDes1 protocol for T4240RDB\n"); } fm_disable_port(FM1_DTSEC5); fm_disable_port(FM1_DTSEC6); for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_SGMII: dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); fm_info_set_mdio(i, dev); break; default: break; } } for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); fm_info_set_mdio(i, dev); break; default: break; } } #if (CONFIG_SYS_NUM_FMAN == 2) if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) { /* SGMII && XFI */ fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6); fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7); fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8); fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR); fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR); } else { puts("Invalid SerDes2 protocol for T4240RDB\n"); } fm_disable_port(FM2_DTSEC5); fm_disable_port(FM2_DTSEC6); for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_SGMII: dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); fm_info_set_mdio(i, dev); break; default: break; } } for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); fm_info_set_mdio(i, dev); break; default: break; } } #endif /* CONFIG_SYS_NUM_FMAN */ cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ return pci_eth_init(bis); }