/* * Miscellaneous intialization */ int misc_init_r (void) { char *fpga_data_str = getenv ("fpgadata"); char *fpga_size_str = getenv ("fpgasize"); void *fpga_data; int fpga_size; int status; volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; int flash_size; /* Remap FLASH according to real size */ flash_size = flash_init (); memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-flash_size & 0xFFFF8000); memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; if (fpga_data_str && fpga_size_str) { fpga_data = (void *) simple_strtoul (fpga_data_str, NULL, 16); fpga_size = simple_strtoul (fpga_size_str, NULL, 10); status = fpga_boot (fpga_data, fpga_size); if (status != 0) { printf ("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_INIT_HIGH: printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_DONE: printf ("(Timeout: DONE not high after programming FPGA)\n "); break; } } } return 0; }
int do_fpga_boot(unsigned char *fpgadata) { unsigned char *dst; int status; int index; int i; ulong len = CONFIG_SYS_MALLOC_LEN; /* * Setup GPIO's for FPGA programming */ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG); GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK); GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA); /* * Save value so no readback is required upon programming */ old_val = *IXP425_GPIO_GPOUTR; /* * First try to decompress fpga image (gzip compressed?) */ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf("Error: Image has to be gzipp'ed!\n"); return -1; } status = fpga_boot(dst, len); if (status != 0) { printf("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_INIT_HIGH: printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_DONE: printf("(Timeout: DONE not high after programming FPGA)\n "); break; } /* display infos on fpgaimage */ index = 15; for (i=0; i<4; i++) { len = dst[index]; printf("FPGA: %s\n", &(dst[index+1])); index += len+3; } putc ('\n'); /* delayed reboot */ for (i=5; i>0; i--) { printf("Rebooting in %2d seconds \r",i); for (index=0;index<1000;index++) udelay(1000); } putc('\n'); do_reset(NULL, 0, 0, NULL); } puts("FPGA: "); /* display infos on fpgaimage */ index = 15; for (i=0; i<4; i++) { len = dst[index]; printf("%s ", &(dst[index+1])); index += len+3; } putc('\n'); free(dst); /* * Reset FPGA */ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET); udelay(10); GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET); return (0); }
int board_early_init_f (void) { #ifndef CONFIG_CPCI405_VER2 int index, len, i; int status; #endif #ifdef FPGA_DEBUG DECLARE_GLOBAL_DATA_PTR; /* set up serial port with default baudrate */ (void) get_clocks (); gd->baudrate = CONFIG_BAUDRATE; serial_init (); console_init_f(); #endif /* * First pull fpga-prg pin low, to disable fpga logic (on version 2 board) */ out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */ out32(GPIO0_OR, 0); /* pull prg low */ /* * Boot onboard FPGA */ #ifndef CONFIG_CPCI405_VER2 if (cpci405_version() == 1) { status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata)); if (status != 0) { /* booting FPGA failed */ #ifndef FPGA_DEBUG DECLARE_GLOBAL_DATA_PTR; /* set up serial port with default baudrate */ (void) get_clocks (); gd->baudrate = CONFIG_BAUDRATE; serial_init (); console_init_f(); #endif printf("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_INIT_HIGH: printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_DONE: printf("(Timeout: DONE not high after programming FPGA)\n "); break; } /* display infos on fpgaimage */ index = 15; for (i=0; i<4; i++) { len = fpgadata[index]; printf("FPGA: %s\n", &(fpgadata[index+1])); index += len+3; } putc ('\n'); /* delayed reboot */ for (i=20; i>0; i--) { printf("Rebooting in %2d seconds \r",i); for (index=0;index<1000;index++) udelay(1000); } putc ('\n'); do_reset(NULL, 0, 0, NULL); } } #endif /* !CONFIG_CPCI405_VER2 */ /* * IRQ 0-15 405GP internally generated; active high; level sensitive * IRQ 16 405GP internally generated; active low; level sensitive * IRQ 17-24 RESERVED * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(uicer, 0x00000000); /* disable all ints */ mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ if (cpci405_version() == 3) { mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */ } else { mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ } mtdcr(uictr, 0x10000000); /* set int trigger levels */ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ return 0; }
int misc_init_r (void) { DECLARE_GLOBAL_DATA_PTR; bd_t *bd = gd->bd; char * tmp; /* Temporary char pointer */ unsigned long cntrl0Reg; #ifdef CONFIG_CPCI405_VER2 unsigned char *dst; ulong len = sizeof(fpgadata); int status; int index; int i; /* * On CPCI-405 version 2 the environment is saved in eeprom! * FPGA can be gzip compressed (malloc) and booted this late. */ if (cpci405_version() >= 2) { /* * Setup GPIO pins (CS6+CS7 as GPIO) */ cntrl0Reg = mfdcr(cntrl0); mtdcr(cntrl0, cntrl0Reg | 0x00300000); dst = malloc(CFG_FPGA_MAX_SIZE); if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); do_reset (NULL, 0, 0, NULL); } status = fpga_boot(dst, len); if (status != 0) { printf("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_INIT_HIGH: printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_DONE: printf("(Timeout: DONE not high after programming FPGA)\n "); break; } /* display infos on fpgaimage */ index = 15; for (i=0; i<4; i++) { len = dst[index]; printf("FPGA: %s\n", &(dst[index+1])); index += len+3; } putc ('\n'); /* delayed reboot */ for (i=20; i>0; i--) { printf("Rebooting in %2d seconds \r",i); for (index=0;index<1000;index++) udelay(1000); } putc ('\n'); do_reset(NULL, 0, 0, NULL); } /* restore gpio/cs settings */ mtdcr(cntrl0, cntrl0Reg); puts("FPGA: "); /* display infos on fpgaimage */ index = 15; for (i=0; i<4; i++) { len = dst[index]; printf("%s ", &(dst[index+1])); index += len+3; } putc ('\n'); free(dst); /* * Reset FPGA via FPGA_DATA pin */ SET_FPGA(FPGA_PRG | FPGA_CLK); udelay(1000); /* wait 1ms */ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); udelay(1000); /* wait 1ms */ if (cpci405_version() == 3) { volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR; volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR; /* * Enable outputs in fpga on version 3 board */ *fpga_mode |= CFG_FPGA_MODE_ENABLE_OUTPUT; /* * Set outputs to 0 */ *leds = 0x00; /* * Reset external DUART */ *fpga_mode |= CFG_FPGA_MODE_DUART_RESET; udelay(100); *fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET); } } else { puts("\n*** U-Boot Version does not match Board Version!\n"); puts("*** CPCI-405 Version 1.x detected!\n"); puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n"); } #else /* CONFIG_CPCI405_VER2 */ /* * Generate last byte of ip-addr from code-plug @ 0xf0000400 */ if (ctermm2()) { char str[32]; unsigned char ipbyte = *(unsigned char *)0xf0000400; /* * Only overwrite ip-addr with allowed values */ if ((ipbyte != 0x00) && (ipbyte != 0xff)) { bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte; sprintf(str, "%ld.%ld.%ld.%ld", (bd->bi_ip_addr & 0xff000000) >> 24, (bd->bi_ip_addr & 0x00ff0000) >> 16, (bd->bi_ip_addr & 0x0000ff00) >> 8, (bd->bi_ip_addr & 0x000000ff)); setenv("ipaddr", str); } }
int misc_init_r (void) { volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4); volatile unsigned char *duart3_mcr = (unsigned char *)((ulong)DUART3_BA + 4); unsigned char *dst; ulong len = sizeof(fpgadata); int status; int index; int i; dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); do_reset (NULL, 0, 0, NULL); } status = fpga_boot(dst, len); if (status != 0) { printf("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_INIT_HIGH: printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_DONE: printf("(Timeout: DONE not high after programming FPGA)\n "); break; } /* display infos on fpgaimage */ index = 15; for (i=0; i<4; i++) { len = dst[index]; printf("FPGA: %s\n", &(dst[index+1])); index += len+3; } putc ('\n'); /* delayed reboot */ for (i=20; i>0; i--) { printf("Rebooting in %2d seconds \r",i); for (index=0;index<1000;index++) udelay(1000); } putc ('\n'); do_reset(NULL, 0, 0, NULL); } puts("FPGA: "); /* display infos on fpgaimage */ index = 15; for (i=0; i<4; i++) { len = dst[index]; printf("%s ", &(dst[index+1])); index += len+3; } putc ('\n'); free(dst); /* * Reset FPGA via FPGA_DATA pin */ SET_FPGA(FPGA_PRG | FPGA_CLK); udelay(1000); /* wait 1ms */ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); udelay(1000); /* wait 1ms */ /* * Reset external DUARTs */ out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */ udelay(10); /* wait 10us */ out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */ udelay(1000); /* wait 1ms */ /* * Enable interrupts in exar duart mcr[3] */ *duart0_mcr = 0x08; *duart1_mcr = 0x08; *duart2_mcr = 0x08; *duart3_mcr = 0x08; return (0); }
int board_early_init_f (void) { int index, len, i; int status; #ifdef FPGA_DEBUG /* set up serial port with default baudrate */ (void) get_clocks (); gd->baudrate = CONFIG_BAUDRATE; serial_init (); console_init_f (); #endif /* * Boot onboard FPGA */ status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata)); if (status != 0) { /* booting FPGA failed */ #ifndef FPGA_DEBUG /* set up serial port with default baudrate */ (void) get_clocks (); gd->baudrate = CONFIG_BAUDRATE; serial_init (); console_init_f (); #endif printf ("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_INIT_HIGH: printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_DONE: printf ("(Timeout: DONE not high after programming FPGA)\n "); break; } /* display infos on fpgaimage */ index = 15; for (i = 0; i < 4; i++) { len = fpgadata[index]; printf ("FPGA: %s\n", &(fpgadata[index + 1])); index += len + 3; } putc ('\n'); /* delayed reboot */ for (i = 20; i > 0; i--) { printf ("Rebooting in %2d seconds \r", i); for (index = 0; index < 1000; index++) udelay (1000); } putc ('\n'); do_reset (NULL, 0, 0, NULL); } /* * IRQ 0-15 405GP internally generated; active high; level sensitive * IRQ 16 405GP internally generated; active low; level sensitive * IRQ 17-24 RESERVED * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive * IRQ 26 (EXT IRQ 1) DUART_A; active high; level sensitive * IRQ 27 (EXT IRQ 2) DUART_B; active high; level sensitive * IRQ 28 (EXT IRQ 3) unused; active low; level sensitive * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive * IRQ 30 (EXT IRQ 5) unused; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr (uicer, 0x00000000); /* disable all ints */ mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ mtdcr (uicpr, 0xFFFFFFB1); /* set int polarities */ mtdcr (uictr, 0x10000000); /* set int trigger levels */ mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 100 us */ mtebc (epcr, 0xb8400000); return 0; }
int misc_init_r (void) { /* adjust flash start and size as well as the offset */ gd->bd->bi_flashstart = 0 - flash_info[0].size; gd->bd->bi_flashoffset= flash_info[0].size - CONFIG_SYS_MONITOR_LEN; #if 0 volatile unsigned short *fpga_mode = (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL); volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); bd_t *bd = gd->bd; char * tmp; /* Temporary char pointer */ unsigned char *dst; ulong len = sizeof(fpgadata); int status; int index; int i; unsigned long CPC0_CR0Reg; dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); do_reset (NULL, 0, 0, NULL); } status = fpga_boot(dst, len); if (status != 0) { printf("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_INIT_HIGH: printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_DONE: printf("(Timeout: DONE not high after programming FPGA)\n "); break; } /* display infos on fpgaimage */ index = 15; for (i=0; i<4; i++) { len = dst[index]; printf("FPGA: %s\n", &(dst[index+1])); index += len+3; } putc ('\n'); /* delayed reboot */ for (i=20; i>0; i--) { printf("Rebooting in %2d seconds \r",i); for (index=0;index<1000;index++) udelay(1000); } putc ('\n'); do_reset(NULL, 0, 0, NULL); } puts("FPGA: "); /* display infos on fpgaimage */ index = 15; for (i=0; i<4; i++) { len = dst[index]; printf("%s ", &(dst[index+1])); index += len+3; } putc ('\n'); free(dst); /* * Reset FPGA via FPGA_DATA pin */ SET_FPGA(FPGA_PRG | FPGA_CLK); udelay(1000); /* wait 1ms */ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); udelay(1000); /* wait 1ms */ #endif #if 0 /* * Enable power on PS/2 interface */ *fpga_mode |= CONFIG_SYS_FPGA_CTRL_PS2_RESET; /* * Enable interrupts in exar duart mcr[3] */ *duart0_mcr = 0x08; *duart1_mcr = 0x08; #endif return (0); }
int misc_init_r(void) { u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL); u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2); u8 *duart0_mcr = (u8 *)(DUART0_BA + 4); u8 *duart1_mcr = (u8 *)(DUART1_BA + 4); unsigned char *dst; ulong len = sizeof(fpgadata); int status; int index; int i; unsigned long CPC0_CR0Reg; char *str; uchar *logo_addr; ulong logo_size; ushort minb, maxb; int result; /* * Setup GPIO pins (CS6+CS7 as GPIO) */ CPC0_CR0Reg = mfdcr(CPC0_CR0); mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000); dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf("GUNZIP ERROR - must RESET board to recover\n"); do_reset(NULL, 0, 0, NULL); } status = fpga_boot(dst, len); if (status != 0) { printf("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: printf("(Timeout: " "INIT not low after asserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_INIT_HIGH: printf("(Timeout: " "INIT not high after deasserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_DONE: printf("(Timeout: " "DONE not high after programming FPGA)\n "); break; } /* display infos on fpgaimage */ index = 15; for (i = 0; i < 4; i++) { len = dst[index]; printf("FPGA: %s\n", &(dst[index+1])); index += len + 3; } putc('\n'); /* delayed reboot */ for (i = 20; i > 0; i--) { printf("Rebooting in %2d seconds \r",i); for (index = 0; index < 1000; index++) udelay(1000); } putc('\n'); do_reset(NULL, 0, 0, NULL); } /* restore gpio/cs settings */ mtdcr(CPC0_CR0, CPC0_CR0Reg); puts("FPGA: "); /* display infos on fpgaimage */ index = 15; for (i = 0; i < 4; i++) { len = dst[index]; printf("%s ", &(dst[index + 1])); index += len + 3; } putc('\n'); free(dst); /* * Reset FPGA via FPGA_DATA pin */ SET_FPGA(FPGA_PRG | FPGA_CLK); udelay(1000); /* wait 1ms */ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); udelay(1000); /* wait 1ms */ /* * Write board revision in FPGA */ out_be16(fpga_ctrl2, (in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f)); /* * Enable power on PS/2 interface (with reset) */ out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET); for (i=0;i<100;i++) udelay(1000); udelay(1000); out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET); /* * Enable interrupts in exar duart mcr[3] */ out_8(duart0_mcr, 0x08); out_8(duart1_mcr, 0x08); /* * Init lcd interface and display logo */ str = getenv("splashimage"); if (str) { logo_addr = (uchar *)simple_strtoul(str, NULL, 16); logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE; } else { logo_addr = logo_bmp; logo_size = sizeof(logo_bmp); } if (gd->board_type >= 6) { result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, regs_13505_640_480_16bpp, sizeof(regs_13505_640_480_16bpp) / sizeof(regs_13505_640_480_16bpp[0]), logo_addr, logo_size); if (result && str) { /* retry with internal image */ logo_addr = logo_bmp; logo_size = sizeof(logo_bmp); lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, regs_13505_640_480_16bpp, sizeof(regs_13505_640_480_16bpp) / sizeof(regs_13505_640_480_16bpp[0]), logo_addr, logo_size); } } else { result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, regs_13806_640_480_16bpp, sizeof(regs_13806_640_480_16bpp) / sizeof(regs_13806_640_480_16bpp[0]), logo_addr, logo_size); if (result && str) { /* retry with internal image */ logo_addr = logo_bmp; logo_size = sizeof(logo_bmp); lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, regs_13806_640_480_16bpp, sizeof(regs_13806_640_480_16bpp) / sizeof(regs_13806_640_480_16bpp[0]), logo_addr, logo_size); } } /* * Reset microcontroller and setup backlight PWM controller */ out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014); for (i=0;i<10;i++) udelay(1000); out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c); minb = 0; maxb = 0xff; str = getenv("lcdbl"); if (str) { minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff; if (str && (*str=',')) { str++; maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff; } else minb = 0; out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb); out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb); printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb); } out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff); /* * fix environment for field updated units */ if (getenv("altbootcmd") == NULL) { setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND); setenv("usbargs", CONFIG_SYS_USB_ARGS); setenv("bootcmd", CONFIG_BOOTCOMMAND); setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND); setenv("bootlimit", CONFIG_SYS_BOOTLIMIT); setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND); saveenv(); } return (0); }
int misc_init_r (void) { unsigned char *dst; ulong len = sizeof(fpgadata); int status; int index; int i; char *str; unsigned long contrast0 = 0xffffffff; dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); do_reset (NULL, 0, 0, NULL); } status = fpga_boot(dst, len); if (status != 0) { printf("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_INIT_HIGH: printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_DONE: printf("(Timeout: DONE not high after programming FPGA)\n "); break; } /* display infos on fpgaimage */ index = 15; for (i=0; i<4; i++) { len = dst[index]; printf("FPGA: %s\n", &(dst[index+1])); index += len+3; } putc ('\n'); /* delayed reboot */ for (i=20; i>0; i--) { printf("Rebooting in %2d seconds \r",i); for (index=0;index<1000;index++) udelay(1000); } putc ('\n'); do_reset(NULL, 0, 0, NULL); } puts("FPGA: "); /* display infos on fpgaimage */ index = 15; for (i=0; i<4; i++) { len = dst[index]; printf("%s ", &(dst[index+1])); index += len+3; } putc ('\n'); free(dst); /* * Reset FPGA via FPGA_INIT pin */ /* setup FPGA_INIT as output */ out_be32((void *)GPIO0_TCR, in_be32((void *)GPIO0_TCR) | FPGA_INIT); out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~FPGA_INIT); /* reset low */ udelay(1000); /* wait 1ms */ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | FPGA_INIT); /* reset high */ udelay(1000); /* wait 1ms */ /* * Write Board revision into FPGA */ out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | (gd->board_type & 0x0003)); /* * Setup and enable EEPROM write protection */ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); /* * Reset touch-screen controller */ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST); udelay(1000); out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_TOUCH_RST); /* * Enable power on PS/2 interface (with reset) */ out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) & ~FPGA_CTRL_PS2_PWR); for (i=0;i<500;i++) udelay(1000); out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | FPGA_CTRL_PS2_PWR); /* * Get contrast value from environment variable */ str = getenv("contrast0"); if (str) { contrast0 = simple_strtol(str, NULL, 16); if (contrast0 > 255) { printf("ERROR: contrast0 value too high (0x%lx)!\n", contrast0); contrast0 = 0xffffffff; } } /* * Init lcd interface and display logo */ str = getenv("bd_type"); if (strcmp(str, "ppc230") == 0) { /* * Switch backlight on */ out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | FPGA_CTRL_VGA0_BL); out_be16(FPGA_BL, 0x0000); lcd_setup(1, 0); lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, regs_13806_1024_768_8bpp, sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]), logo_bmp_1024, sizeof(logo_bmp_1024)); } else if (strcmp(str, "ppc220") == 0) { /* * Switch backlight on */ out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) & ~FPGA_CTRL_VGA0_BL); out_be16(FPGA_BL, 0x0000); lcd_setup(1, 0); lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, regs_13806_640_480_16bpp, sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]), logo_bmp_640, sizeof(logo_bmp_640)); } else if (strcmp(str, "ppc215") == 0) { /* * Set default display contrast voltage */ if (contrast0 == 0xffffffff) { out_be16(FPGA_CTR, 0x0082); } else { out_be16(FPGA_CTR, contrast0); } out_be16(FPGA_BL, 0xffff); /* * Switch backlight on */ out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | FPGA_CTRL_VGA0_BL | FPGA_CTRL_VGA0_BL_MODE); /* * Set lcd clock (small epson) */ out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | LCD_CLK_06250); udelay(100); /* wait for 100 us */ lcd_setup(0, 1); lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, regs_13705_320_240_8bpp, sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]), logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp)); } else if (strcmp(str, "ppc210") == 0) { /* * Set default display contrast voltage */ if (contrast0 == 0xffffffff) { out_be16(FPGA_CTR, 0x0060); } else { out_be16(FPGA_CTR, contrast0); } out_be16(FPGA_BL, 0xffff); /* * Switch backlight on */ out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | FPGA_CTRL_VGA0_BL | FPGA_CTRL_VGA0_BL_MODE); /* * Set lcd clock (small epson), enable 1-wire interface */ out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | LCD_CLK_08330 | FPGA_CTRL_OW_ENABLE); lcd_setup(0, 1); lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, regs_13704_320_240_4bpp, sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), logo_bmp_320, sizeof(logo_bmp_320)); #ifdef CONFIG_VIDEO_SM501 } else { pci_dev_t devbusfn; /* * Is SM501 connected (ppc221/ppc231)? */ devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); if (devbusfn != -1) { puts("VGA: SM501 with 8 MB "); if (strcmp(str, "ppc221") == 0) { printf("(800*600, %dbpp)\n", BPP); out_be16(FPGA_BL, 0x002d); /* max. allowed brightness */ } else if (strcmp(str, "ppc231") == 0) { printf("(1024*768, %dbpp)\n", BPP); out_be16(FPGA_BL, 0x0000); } else { printf("Unsupported bd_type defined (%s) -> No display configured!\n", str); return 0; } } else { printf("Unsupported bd_type defined (%s) -> No display configured!\n", str); return 0; } #endif /* CONFIG_VIDEO_SM501 */ } cf_enable(); return (0); }
int board_early_init_f (void) { int index, len, i; int status; #ifdef FPGA_DEBUG /* set up serial port with default baudrate */ (void) get_clocks (); gd->baudrate = CONFIG_BAUDRATE; serial_init (); console_init_f (); #endif /* * Boot onboard FPGA */ /* first try 40er image */ gd->board_type = 40; status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata)); if (status != 0) { /* try xl30er image */ gd->board_type = 30; status = fpga_boot ((unsigned char *) fpgadata_xl30, sizeof (fpgadata_xl30)); if (status != 0) { /* booting FPGA failed */ #ifndef FPGA_DEBUG /* set up serial port with default baudrate */ (void) get_clocks (); gd->baudrate = CONFIG_BAUDRATE; serial_init (); console_init_f (); #endif printf ("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_INIT_HIGH: printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_DONE: printf ("(Timeout: DONE not high after programming FPGA)\n "); break; } /* display infos on fpgaimage */ index = 15; for (i = 0; i < 4; i++) { len = fpgadata[index]; printf ("FPGA: %s\n", &(fpgadata[index + 1])); index += len + 3; } putc ('\n'); /* delayed reboot */ for (i = 20; i > 0; i--) { printf ("Rebooting in %2d seconds \r", i); for (index = 0; index < 1000; index++) udelay (1000); } putc ('\n'); do_reset (NULL, 0, 0, NULL); } } /* * IRQ 0-15 405GP internally generated; active high; level sensitive * IRQ 16 405GP internally generated; active low; level sensitive * IRQ 17-24 RESERVED * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtdcr (UIC0ER, 0x00000000); /* disable all ints */ mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */ mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ out_be16((void *)0xf03000ec, 0x0fff); /* enable interrupts in fpga */ return 0; }
int misc_init_r(void) { unsigned char *dst; unsigned char fctr; ulong len = sizeof(fpgadata); int status; int index; int i; /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf("GUNZIP ERROR - must RESET board to recover\n"); do_reset(NULL, 0, 0, NULL); } status = fpga_boot(dst, len); if (status != 0) { printf("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: printf("(Timeout: INIT not low " "after asserting PROGRAM*)\n"); break; case ERROR_FPGA_PRG_INIT_HIGH: printf("(Timeout: INIT not high " "after deasserting PROGRAM*)\n"); break; case ERROR_FPGA_PRG_DONE: printf("(Timeout: DONE not high " "after programming FPGA)\n"); break; } /* display infos on fpgaimage */ index = 15; for (i=0; i<4; i++) { len = dst[index]; printf("FPGA: %s\n", &(dst[index+1])); index += len+3; } putc ('\n'); /* delayed reboot */ for (i=20; i>0; i--) { printf("Rebooting in %2d seconds \r",i); for (index=0;index<1000;index++) udelay(1000); } putc('\n'); do_reset(NULL, 0, 0, NULL); } puts("FPGA: "); /* display infos on fpgaimage */ index = 15; for (i=0; i<4; i++) { len = dst[index]; printf("%s ", &(dst[index+1])); index += len+3; } putc('\n'); free(dst); /* * Reset FPGA via FPGA_DATA pin */ SET_FPGA(FPGA_PRG | FPGA_CLK); udelay(1000); /* wait 1ms */ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); udelay(1000); /* wait 1ms */ /* * Reset external DUARTs */ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); udelay(10); out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); udelay(1000); /* * Set NAND-FLASH GPIO signals to default */ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE)); out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE); /* * Setup EEPROM write protection */ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP); /* * Enable interrupts in exar duart mcr[3] */ out_8((void *)DUART0_BA + 4, 0x08); out_8((void *)DUART1_BA + 4, 0x08); /* * Enable auto RS485 mode in 2nd external uart */ out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */ fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */ fctr |= 0x08; /* enable RS485 mode */ out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */ out_8((void *)DUART1_BA + 3, 0); /* write LCR */ /* * Init magnetic couplers */ if (!getenv("noinitcoupler")) { init_coupler(CAN0_BA); init_coupler(CAN1_BA); } return 0; }
int board_early_init_f (void) { unsigned long cntrl0Reg; int index, len, i; int status; /* * Setup GPIO pins */ cntrl0Reg = mfdcr (cntrl0) & 0xf0001fff; cntrl0Reg |= 0x0070f000; mtdcr (cntrl0, cntrl0Reg); #ifdef FPGA_DEBUG /* set up serial port with default baudrate */ (void) get_clocks (); gd->baudrate = CONFIG_BAUDRATE; serial_init (); console_init_f (); #endif /* * Boot onboard FPGA */ status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata)); if (status != 0) { /* booting FPGA failed */ #ifndef FPGA_DEBUG /* set up serial port with default baudrate */ (void) get_clocks (); gd->baudrate = CONFIG_BAUDRATE; serial_init (); console_init_f (); #endif printf ("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_INIT_HIGH: printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_DONE: printf ("(Timeout: DONE not high after programming FPGA)\n "); break; } /* display infos on fpgaimage */ index = 15; for (i = 0; i < 4; i++) { len = fpgadata[index]; printf ("FPGA: %s\n", &(fpgadata[index + 1])); index += len + 3; } putc ('\n'); /* delayed reboot */ for (i = 20; i > 0; i--) { printf ("Rebooting in %2d seconds \r", i); for (index = 0; index < 1000; index++) udelay (1000); } putc ('\n'); do_reset (NULL, 0, 0, NULL); } /* * Setup port pins for normal operation */ out_be32 ((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */ out_be32 ((void *)GPIO0_TCR, 0x07038100); /* setup for output */ out_be32 ((void *)GPIO0_OR, 0x07030100); /* set output pins to high (default) */ /* * IRQ 0-15 405GP internally generated; active high; level sensitive * IRQ 16 405GP internally generated; active low; level sensitive * IRQ 17-24 RESERVED * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr (uicer, 0x00000000); /* disable all ints */ mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */ mtdcr (uictr, 0x10000000); /* set int trigger levels */ mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ return 0; }
int misc_init_r (void) { unsigned long CPC0_CR0Reg; /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; #if defined(CONFIG_CPCI405_VER2) { unsigned char *dst; ulong len = sizeof(fpgadata); int status; int index; int i; /* * On CPCI-405 version 2 the environment is saved in eeprom! * FPGA can be gzip compressed (malloc) and booted this late. */ if (cpci405_version() >= 2) { /* * Setup GPIO pins (CS6+CS7 as GPIO) */ CPC0_CR0Reg = mfdcr(CPC0_CR0); mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000); dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf("GUNZIP ERROR - must RESET board to recover\n"); do_reset(NULL, 0, 0, NULL); } status = fpga_boot(dst, len); if (status != 0) { printf("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: printf("(Timeout: INIT not low after " "asserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_INIT_HIGH: printf("(Timeout: INIT not high after " "deasserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_DONE: printf("(Timeout: DONE not high after " "programming FPGA)\n "); break; } /* display infos on fpgaimage */ index = 15; for (i = 0; i < 4; i++) { len = dst[index]; printf("FPGA: %s\n", &(dst[index + 1])); index += len + 3; } putc('\n'); /* delayed reboot */ for (i = 20; i > 0; i--) { printf("Rebooting in %2d seconds \r", i); for (index = 0; index < 1000; index++) udelay(1000); } putc('\n'); do_reset(NULL, 0, 0, NULL); } /* restore gpio/cs settings */ mtdcr(CPC0_CR0, CPC0_CR0Reg); puts("FPGA: "); /* display infos on fpgaimage */ index = 15; for (i = 0; i < 4; i++) { len = dst[index]; printf("%s ", &(dst[index + 1])); index += len + 3; } putc('\n'); free(dst); /* * Reset FPGA via FPGA_DATA pin */ SET_FPGA(FPGA_PRG | FPGA_CLK); udelay(1000); /* wait 1ms */ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); udelay(1000); /* wait 1ms */ #if defined(CONFIG_CPCI405_6U) #error HIER GETH ES WEITER MIT IO ACCESSORS if (cpci405_version() == 3) { /* * Enable outputs in fpga on version 3 board */ out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) | CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT); /* * Set outputs to 0 */ out_8((void*)CONFIG_SYS_LED_ADDR, 0x00); /* * Reset external DUART */ out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) | CONFIG_SYS_FPGA_MODE_DUART_RESET); udelay(100); out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) & ~CONFIG_SYS_FPGA_MODE_DUART_RESET); } #endif } else { puts("\n*** U-Boot Version does not match Board Version!\n"); puts("*** CPCI-405 Version 1.x detected!\n"); puts("*** Please use correct U-Boot version " "(CPCI405 instead of CPCI4052)!\n\n"); } } #else /* CONFIG_CPCI405_VER2 */ if (cpci405_version() >= 2) { puts("\n*** U-Boot Version does not match Board Version!\n"); puts("*** CPCI-405 Board Version 2.x detected!\n"); puts("*** Please use correct U-Boot version " "(CPCI4052 instead of CPCI405)!\n\n"); } #endif /* CONFIG_CPCI405_VER2 */ /* * Select cts (and not dsr) on uart1 */ CPC0_CR0Reg = mfdcr(CPC0_CR0); mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); return 0; }
int misc_init_r (void) { unsigned char *dst; ulong len = sizeof(fpgadata); int status; int index; int i; unsigned int *ptr; unsigned int *magic; /* * On PCI-405 the environment is saved in eeprom! * FPGA can be gzip compressed (malloc) and booted this late. */ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); do_reset (NULL, 0, 0, NULL); } status = fpga_boot(dst, len); if (status != 0) { printf("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_INIT_HIGH: printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_DONE: printf("(Timeout: DONE not high after programming FPGA)\n "); break; } /* display infos on fpgaimage */ index = 15; for (i=0; i<4; i++) { len = dst[index]; printf("FPGA: %s\n", &(dst[index+1])); index += len+3; } putc ('\n'); /* delayed reboot */ for (i=20; i>0; i--) { printf("Rebooting in %2d seconds \r",i); for (index=0; index<1000; index++) udelay(1000); } putc ('\n'); do_reset(NULL, 0, 0, NULL); } puts("FPGA: "); /* display infos on fpgaimage */ index = 15; for (i=0; i<4; i++) { len = dst[index]; printf("%s ", &(dst[index+1])); index += len+3; } putc ('\n'); /* * Reset FPGA via FPGA_DATA pin */ SET_FPGA(FPGA_PRG | FPGA_CLK); udelay(1000); /* wait 1ms */ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); udelay(1000); /* wait 1ms */ /* * Check if magic for pci reconfig is written */ magic = (unsigned int *)0x00000004; if (*magic == PCI_RECONFIG_MAGIC) { /* * Rewrite pci config regs (only after soft-reset with magic set) */ ptr = (unsigned int *)PCI_REGS_ADDR; if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) { puts("Restoring PCI Configurations Regs!\n"); ptr = (unsigned int *)PCI_REGS_ADDR + 1; for (i=0; i<0x40; i+=4) { pci_write_config_dword(PCIDEVID_405GP, i, *ptr++); } } mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ *magic = 0; /* clear pci reconfig magic again */ } /* * Decrease PLB latency timeout and reduce priority of the PCI bridge master */ #define PCI0_BRDGOPT1 0x4a pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20); #define PLB0_ACR 0x87 /* * Enable fairness and high bus utilization */ mtdcr(PLB0_ACR, 0x98000000); free(dst); return (0); }
int misc_init_r (void) { unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); unsigned short *lcd_contrast = (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4); unsigned short *lcd_backlight = (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6); unsigned char *dst; ulong len = sizeof(fpgadata); int status; int index; int i; char *str; dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); do_reset (NULL, 0, 0, NULL); } status = fpga_boot(dst, len); if (status != 0) { printf("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_INIT_HIGH: printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_DONE: printf("(Timeout: DONE not high after programming FPGA)\n "); break; } /* display infos on fpgaimage */ index = 15; for (i=0; i<4; i++) { len = dst[index]; printf("FPGA: %s\n", &(dst[index+1])); index += len+3; } putc ('\n'); /* delayed reboot */ for (i=20; i>0; i--) { printf("Rebooting in %2d seconds \r",i); for (index=0;index<1000;index++) udelay(1000); } putc ('\n'); do_reset(NULL, 0, 0, NULL); } puts("FPGA: "); /* display infos on fpgaimage */ index = 15; for (i=0; i<4; i++) { len = dst[index]; printf("%s ", &(dst[index+1])); index += len+3; } putc ('\n'); free(dst); /* * Reset FPGA via FPGA_INIT pin */ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT); /* reset low */ udelay(1000); /* wait 1ms */ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT); /* reset high */ udelay(1000); /* wait 1ms */ /* * Reset external DUARTs */ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */ udelay(10); /* wait 10us */ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */ udelay(1000); /* wait 1ms */ /* * Set NAND-FLASH GPIO signals to default */ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE)); out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE); /* * Setup EEPROM write protection */ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP); /* * Enable interrupts in exar duart mcr[3] */ out_8(duart0_mcr, 0x08); out_8(duart1_mcr, 0x08); /* * Init lcd interface and display logo */ str = getenv("bd_type"); if (strcmp(str, "voh405_bw") == 0) { lcd_setup(0, 1); lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, regs_13704_320_240_4bpp, sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), logo_bmp_320, sizeof(logo_bmp_320)); } else if (strcmp(str, "voh405_bwbw") == 0) { lcd_setup(0, 1); lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, regs_13704_320_240_4bpp, sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), logo_bmp_320, sizeof(logo_bmp_320)); lcd_setup(1, 1); lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, regs_13806_320_240_4bpp, sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]), logo_bmp_320, sizeof(logo_bmp_320)); } else if (strcmp(str, "voh405_bwc") == 0) { lcd_setup(0, 1); lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, regs_13704_320_240_4bpp, sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), logo_bmp_320, sizeof(logo_bmp_320)); lcd_setup(1, 0); lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, regs_13806_640_480_16bpp, sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]), logo_bmp_640, sizeof(logo_bmp_640)); } else { printf("Unsupported bd_type defined (%s) -> No display configured!\n", str); return 0; } /* * Set invert bit in small lcd controller */ out_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2), in_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2)) | 0x01); /* * Set default contrast voltage on epson vga controller */ out_be16(lcd_contrast, 0x4646); /* * Enable backlight */ out_be16(lcd_backlight, 0xffff); /* * Enable external I2C bus */ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_IIC_ON); return (0); }