static int fs_enet_open(struct net_device *dev) { struct fs_enet_private *fep = netdev_priv(dev); int r; int err; /* to initialize the fep->cur_rx,... */ /* not doing this, will cause a crash in fs_enet_rx_napi */ fs_init_bds(fep->ndev); if (fep->fpi->use_napi) napi_enable(&fep->napi); /* Install our interrupt handler. */ r = fs_request_irq(dev, fep->interrupt, "fs_enet-mac", fs_enet_interrupt); if (r != 0) { printk(KERN_ERR DRV_MODULE_NAME ": %s Could not allocate FS_ENET IRQ!", dev->name); if (fep->fpi->use_napi) napi_disable(&fep->napi); return -EINVAL; } err = fs_init_phy(dev); if (err) { if (fep->fpi->use_napi) napi_disable(&fep->napi); return err; } phy_start(fep->phydev); return 0; }
static int fs_enet_open(struct net_device *dev) { struct fs_enet_private *fep = netdev_priv(dev); int r; int err; /* Install our interrupt handler. */ r = fs_request_irq(dev, fep->interrupt, "fs_enet-mac", fs_enet_interrupt); if (r != 0) { printk(KERN_ERR DRV_MODULE_NAME ": %s Could not allocate FS_ENET IRQ!", dev->name); return -EINVAL; } fs_init_bds(dev); err = fs_init_phy(dev); if(err) return err; phy_start(fep->phydev); return 0; }
static int fs_enet_open(struct net_device *dev) { struct fs_enet_private *fep = netdev_priv(dev); int r; int err; /* to initialize the fep->cur_rx,... */ /* not doing this, will cause a crash in fs_enet_rx_napi */ fs_init_bds(fep->ndev); if (fep->fpi->use_napi) napi_enable(&fep->napi); /* Install our interrupt handler. */ r = request_irq(fep->interrupt, fs_enet_interrupt, IRQF_SHARED, "fs_enet-mac", dev); if (r != 0) { dev_err(fep->dev, "Could not allocate FS_ENET IRQ!"); if (fep->fpi->use_napi) napi_disable(&fep->napi); return -EINVAL; } err = fs_init_phy(dev); if (err) { free_irq(fep->interrupt, dev); if (fep->fpi->use_napi) napi_disable(&fep->napi); return err; } phy_start(fep->phydev); netif_start_queue(dev); return 0; }
static void restart(struct net_device *dev) { struct fs_enet_private *fep = netdev_priv(dev); const struct fs_platform_info *fpi = fep->fpi; fcc_t __iomem *fccp = fep->fcc.fccp; fcc_c_t __iomem *fcccp = fep->fcc.fcccp; fcc_enet_t __iomem *ep = fep->fcc.ep; dma_addr_t rx_bd_base_phys, tx_bd_base_phys; u16 paddrh, paddrm, paddrl; const unsigned char *mac; int i; C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT); /* clear everything (slow & steady does it) */ for (i = 0; i < sizeof(*ep); i++) out_8((u8 __iomem *)ep + i, 0); /* get physical address */ rx_bd_base_phys = fep->ring_mem_addr; tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring; /* point to bds */ W32(ep, fen_genfcc.fcc_rbase, rx_bd_base_phys); W32(ep, fen_genfcc.fcc_tbase, tx_bd_base_phys); /* Set maximum bytes per receive buffer. * It must be a multiple of 32. */ W16(ep, fen_genfcc.fcc_mrblr, PKT_MAXBLR_SIZE); W32(ep, fen_genfcc.fcc_rstate, (CPMFCR_GBL | CPMFCR_EB) << 24); W32(ep, fen_genfcc.fcc_tstate, (CPMFCR_GBL | CPMFCR_EB) << 24); /* Allocate space in the reserved FCC area of DPRAM for the * internal buffers. No one uses this space (yet), so we * can do this. Later, we will add resource management for * this area. */ W16(ep, fen_genfcc.fcc_riptr, fpi->dpram_offset); W16(ep, fen_genfcc.fcc_tiptr, fpi->dpram_offset + 32); W16(ep, fen_padptr, fpi->dpram_offset + 64); /* fill with special symbol... */ memset_io(fep->fcc.mem + fpi->dpram_offset + 64, 0x88, 32); W32(ep, fen_genfcc.fcc_rbptr, 0); W32(ep, fen_genfcc.fcc_tbptr, 0); W32(ep, fen_genfcc.fcc_rcrc, 0); W32(ep, fen_genfcc.fcc_tcrc, 0); W16(ep, fen_genfcc.fcc_res1, 0); W32(ep, fen_genfcc.fcc_res2, 0); /* no CAM */ W32(ep, fen_camptr, 0); /* Set CRC preset and mask */ W32(ep, fen_cmask, 0xdebb20e3); W32(ep, fen_cpres, 0xffffffff); W32(ep, fen_crcec, 0); /* CRC Error counter */ W32(ep, fen_alec, 0); /* alignment error counter */ W32(ep, fen_disfc, 0); /* discard frame counter */ W16(ep, fen_retlim, 15); /* Retry limit threshold */ W16(ep, fen_pper, 0); /* Normal persistence */ /* set group address */ W32(ep, fen_gaddrh, fep->fcc.gaddrh); W32(ep, fen_gaddrl, fep->fcc.gaddrh); /* Clear hash filter tables */ W32(ep, fen_iaddrh, 0); W32(ep, fen_iaddrl, 0); /* Clear the Out-of-sequence TxBD */ W16(ep, fen_tfcstat, 0); W16(ep, fen_tfclen, 0); W32(ep, fen_tfcptr, 0); W16(ep, fen_mflr, PKT_MAXBUF_SIZE); /* maximum frame length register */ W16(ep, fen_minflr, PKT_MINBUF_SIZE); /* minimum frame length register */ /* set address */ mac = dev->dev_addr; paddrh = ((u16)mac[5] << 8) | mac[4]; paddrm = ((u16)mac[3] << 8) | mac[2]; paddrl = ((u16)mac[1] << 8) | mac[0]; W16(ep, fen_paddrh, paddrh); W16(ep, fen_paddrm, paddrm); W16(ep, fen_paddrl, paddrl); W16(ep, fen_taddrh, 0); W16(ep, fen_taddrm, 0); W16(ep, fen_taddrl, 0); W16(ep, fen_maxd1, 1520); /* maximum DMA1 length */ W16(ep, fen_maxd2, 1520); /* maximum DMA2 length */ /* Clear stat counters, in case we ever enable RMON */ W32(ep, fen_octc, 0); W32(ep, fen_colc, 0); W32(ep, fen_broc, 0); W32(ep, fen_mulc, 0); W32(ep, fen_uspc, 0); W32(ep, fen_frgc, 0); W32(ep, fen_ospc, 0); W32(ep, fen_jbrc, 0); W32(ep, fen_p64c, 0); W32(ep, fen_p65c, 0); W32(ep, fen_p128c, 0); W32(ep, fen_p256c, 0); W32(ep, fen_p512c, 0); W32(ep, fen_p1024c, 0); W16(ep, fen_rfthr, 0); /* Suggested by manual */ W16(ep, fen_rfcnt, 0); W16(ep, fen_cftype, 0); fs_init_bds(dev); /* adjust to speed (for RMII mode) */ if (fpi->use_rmii) { if (fep->phydev->speed == 100) C8(fcccp, fcc_gfemr, 0x20); else S8(fcccp, fcc_gfemr, 0x20); } fcc_cr_cmd(fep, CPM_CR_INIT_TRX); /* clear events */ W16(fccp, fcc_fcce, 0xffff); /* Enable interrupts we wish to service */ W16(fccp, fcc_fccm, FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB); /* Set GFMR to enable Ethernet operating mode */ W32(fccp, fcc_gfmr, FCC_GFMR_TCI | FCC_GFMR_MODE_ENET); /* set sync/delimiters */ W16(fccp, fcc_fdsr, 0xd555); W32(fccp, fcc_fpsmr, FCC_PSMR_ENCRC); if (fpi->use_rmii) S32(fccp, fcc_fpsmr, FCC_PSMR_RMII); /* adjust to duplex mode */ if (fep->phydev->duplex) S32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB); else C32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB); /* Restore multicast and promiscuous settings */ set_multicast_list(dev); S32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT); }
/* * This function is called to start or restart the FEC during a link * change. This only happens when switching between half and full * duplex. */ static void restart(struct net_device *dev) { struct fs_enet_private *fep = netdev_priv(dev); scc_t __iomem *sccp = fep->scc.sccp; scc_enet_t __iomem *ep = fep->scc.ep; const struct fs_platform_info *fpi = fep->fpi; u16 paddrh, paddrm, paddrl; const unsigned char *mac; int i; C32(sccp, scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); /* clear everything (slow & steady does it) */ for (i = 0; i < sizeof(*ep); i++) __fs_out8((u8 __iomem *)ep + i, 0); /* point to bds */ W16(ep, sen_genscc.scc_rbase, fep->ring_mem_addr); W16(ep, sen_genscc.scc_tbase, fep->ring_mem_addr + sizeof(cbd_t) * fpi->rx_ring); /* Initialize function code registers for big-endian. */ #ifndef CONFIG_NOT_COHERENT_CACHE W8(ep, sen_genscc.scc_rfcr, SCC_EB | SCC_GBL); W8(ep, sen_genscc.scc_tfcr, SCC_EB | SCC_GBL); #else W8(ep, sen_genscc.scc_rfcr, SCC_EB); W8(ep, sen_genscc.scc_tfcr, SCC_EB); #endif /* Set maximum bytes per receive buffer. * This appears to be an Ethernet frame size, not the buffer * fragment size. It must be a multiple of four. */ W16(ep, sen_genscc.scc_mrblr, 0x5f0); /* Set CRC preset and mask. */ W32(ep, sen_cpres, 0xffffffff); W32(ep, sen_cmask, 0xdebb20e3); W32(ep, sen_crcec, 0); /* CRC Error counter */ W32(ep, sen_alec, 0); /* alignment error counter */ W32(ep, sen_disfc, 0); /* discard frame counter */ W16(ep, sen_pads, 0x8888); /* Tx short frame pad character */ W16(ep, sen_retlim, 15); /* Retry limit threshold */ W16(ep, sen_maxflr, 0x5ee); /* maximum frame length register */ W16(ep, sen_minflr, PKT_MINBUF_SIZE); /* minimum frame length register */ W16(ep, sen_maxd1, 0x000005f0); /* maximum DMA1 length */ W16(ep, sen_maxd2, 0x000005f0); /* maximum DMA2 length */ /* Clear hash tables. */ W16(ep, sen_gaddr1, 0); W16(ep, sen_gaddr2, 0); W16(ep, sen_gaddr3, 0); W16(ep, sen_gaddr4, 0); W16(ep, sen_iaddr1, 0); W16(ep, sen_iaddr2, 0); W16(ep, sen_iaddr3, 0); W16(ep, sen_iaddr4, 0); /* set address */ mac = dev->dev_addr; paddrh = ((u16) mac[5] << 8) | mac[4]; paddrm = ((u16) mac[3] << 8) | mac[2]; paddrl = ((u16) mac[1] << 8) | mac[0]; W16(ep, sen_paddrh, paddrh); W16(ep, sen_paddrm, paddrm); W16(ep, sen_paddrl, paddrl); W16(ep, sen_pper, 0); W16(ep, sen_taddrl, 0); W16(ep, sen_taddrm, 0); W16(ep, sen_taddrh, 0); fs_init_bds(dev); scc_cr_cmd(fep, CPM_CR_INIT_TRX); W16(sccp, scc_scce, 0xffff); /* Enable interrupts we wish to service. */ W16(sccp, scc_sccm, SCCE_ENET_TXE | SCCE_ENET_RXF | SCCE_ENET_TXB); /* Set GSMR_H to enable all normal operating modes. * Set GSMR_L to enable Ethernet to MC68160. */ W32(sccp, scc_gsmrh, 0); W32(sccp, scc_gsmrl, SCC_GSMRL_TCI | SCC_GSMRL_TPL_48 | SCC_GSMRL_TPP_10 | SCC_GSMRL_MODE_ENET); /* Set sync/delimiters. */ W16(sccp, scc_dsr, 0xd555); /* Set processing mode. Use Ethernet CRC, catch broadcast, and * start frame search 22 bit times after RENA. */ W16(sccp, scc_psmr, SCC_PSMR_ENCRC | SCC_PSMR_NIB22); /* Set full duplex mode if needed */ if (fep->phydev->duplex) S16(sccp, scc_psmr, SCC_PSMR_LPB | SCC_PSMR_FDE); S32(sccp, scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); }