static int board_init_r(void) { const unsigned int flashbase = CFG_FLASH_BASE; const u8 flash_esel = e500_find_tlb_idx((void *)flashbase, 1); checkboard(); /* Map the whole boot flash */ fsl_set_lbc_br(0, BR_PHYS_ADDR(CFG_FLASH_BASE_PHYS) | BR_PS_16 | BR_V); fsl_set_lbc_or(0, 0xff000ff7); /* Flush d-cache and invalidate i-cache of any FLASH data */ flush_dcache(); invalidate_icache(); /* invalidate existing TLB entry for flash */ e500_disable_tlb(flash_esel); /* * Remap Boot flash region to caching-inhibited * so that flash can be erased properly. */ e500_set_tlb(1, flashbase, CFG_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_16M, 1); fsl_l2_cache_init(); return 0; }
static int p1010rdb_board_init_r(void) { const uint32_t flashbase = CFG_BOOT_BLOCK; const u8 flash_esel = e500_find_tlb_idx((void *)flashbase, 1); /* Flush d-cache and invalidate i-cache of any FLASH data */ flush_dcache(); invalidate_icache(); /* invalidate existing TLB entry for flash */ e500_disable_tlb(flash_esel); /* * Remap Boot flash region to caching-inhibited * so that flash can be erased properly. */ e500_set_tlb(1, flashbase, CFG_BOOT_BLOCK_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); fsl_l2_cache_init(); return 0; }
static int da923rc_board_init_r(void) { void __iomem *lbc = LBC_BASE_ADDR; void __iomem *ecm = IOMEM(MPC85xx_ECM_ADDR); void __iomem *pci = IOMEM(PCI1_BASE_ADDR); const unsigned int flashbase = (BOOT_BLOCK + 0x2000000); uint8_t flash_esel; da923rc_boardinfo_get(&binfo); flush_dcache(); invalidate_icache(); /* Clear LBC error interrupts */ out_be32(lbc + FSL_LBC_LTESR_OFFSET, 0xffffffff); /* Enable LBC error interrupts */ out_be32(lbc + FSL_LBC_LTEIR_OFFSET, 0xffffffff); /* Clear ecm errors */ out_be32(ecm + MPC85xx_ECM_EEDR_OFFSET, 0xffffffff); /* Enable ecm errors */ out_be32(ecm + MPC85xx_ECM_EEER_OFFSET, 0xffffffff); /* Re-map boot flash */ fsl_set_lbc_br(0, BR_PHYS_ADDR(0xfe000000) | BR_PS_16 | BR_V); fsl_set_lbc_or(0, 0xfe006e21); /* Invalidate TLB entry for boot block */ flash_esel = e500_find_tlb_idx((void *)flashbase, 1); e500_disable_tlb(flash_esel); flash_esel = e500_find_tlb_idx((void *)(flashbase + 0x1000000), 1); e500_disable_tlb(flash_esel); /* Boot block back to cache inhibited. */ e500_set_tlb(1, BOOT_BLOCK + (2 * 0x1000000), BOOT_BLOCK + (2 * 0x1000000), MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G | MAS2_M, 0, 2, BOOKE_PAGESZ_16M, 1); e500_set_tlb(1, BOOT_BLOCK + (3 * 0x1000000), BOOT_BLOCK + (3 * 0x1000000), MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G | MAS2_M, 0, 3, BOOKE_PAGESZ_16M, 1); fsl_l2_cache_init(); fsl_enable_gpiout(); /* Enable NOR low voltage programming (gpio 2) and write (gpio 3). */ gpio_set_value(2, 1); gpio_set_value(3, 1); /* Enable write to NAND flash */ if (binfo.bid == BOARD_TYPE_GBX460) { /* Map CPLD */ fsl_set_lbc_br(3, BR_PHYS_ADDR(0xfc010000) | BR_PS_16 | BR_V); fsl_set_lbc_or(3, 0xffffe001); /* Enable all reset */ out_be16(IOMEM(0xfc010044), 0xffff); gpio_set_value(6, 1); } /* Board reset and PHY reset. Disable CS3. */ if (binfo.bid == BOARD_TYPE_DA923) { gpio_set_value(0, 0); gpio_set_value(1, 1); /* De-assert Board reset */ udelay(1000); gpio_set_value(0, 1); } /* Enable PCI error reporting */ out_be32(pci + 0xe00, 0x80000040); out_be32(pci + 0xe08, 0x6bf); out_be32(pci + 0xe0c, 0xbb1fa001); /* 32-bytes cacheline size */ out_be32(pci, 0x8000000c); out_le32(pci + 4, 0x00008008); return 0; }