static int fsl_usb_host_init_ext(struct platform_device *pdev)
{
static void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
int ret;
struct clk *usb_clk;
/* The PLL's power and output to usb for host 1
* is totally controlled by IC, so the Software only needs
* to enable them at initializtion. */
__raw_writel(BM_ANADIG_USB2_PLL_480_CTRL_BYPASS,
anatop_base_addr + HW_ANADIG_USB2_PLL_480_CTRL_CLR);
__raw_writel(BM_ANADIG_USB2_PLL_480_CTRL_ENABLE \
| BM_ANADIG_USB2_PLL_480_CTRL_POWER \
| BM_ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS, \
anatop_base_addr + HW_ANADIG_USB2_PLL_480_CTRL_SET);
usb_clk = clk_get(NULL, "usboh3_clk");
clk_enable(usb_clk);
usb_oh3_clk = usb_clk;
ret = fsl_usb_host_init(pdev);
if (ret) {
printk(KERN_ERR "host1 init fails......\n");
clk_disable(usb_oh3_clk);
clk_put(usb_oh3_clk);
return ret;
}
usbh1_internal_phy_clock_gate(true);
usb_phy_enable(pdev->dev.platform_data);
return 0;
}
static int fsl_usb_host_init_ext(struct platform_device *pdev)
{
int ret = 0;
struct clk *usb_clk;
usb_clk = clk_get(NULL, "usboh3_clk");
clk_enable(usb_clk);
clk_put(usb_clk);
/* on mx53, there is a hardware limitation that when switch the host2's clk mode
* ,usb phy1 clk must be on, after finish switching this clk can be off */
if (cpu_is_mx53()) {
usb_clk = clk_get(NULL, "usb_phy1_clk");
clk_enable(usb_clk);
clk_put(usb_clk);
}
ret = fsl_usb_host_init(pdev);
if (cpu_is_mx53()) {
usb_clk = clk_get(NULL, "usb_phy1_clk");
clk_disable(usb_clk);
clk_put(usb_clk);
}
/* setback USBH2_STP to be function */
mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
return ret;
}
static int fsl_usb_host_init_ext(struct platform_device *pdev)
{
iomux_v3_cfg_t usbh1stp_func = MX51_PAD_USBH1_STP__USBH1_STP;
int ret;
struct clk *usb_clk;
/* the usb_ahb_clk will be enabled in usb_otg_init */
usb_ahb_clk = clk_get(NULL, "usb_ahb_clk");
if (cpu_is_mx53()) {
usb_clk = clk_get(NULL, "usboh3_clk");
clk_enable(usb_clk);
usb_oh3_clk = usb_clk;
usb_clk = clk_get(NULL, "usb_phy2_clk");
clk_enable(usb_clk);
usb_phy2_clk = usb_clk;
} else if (cpu_is_mx50()) {
usb_clk = clk_get(NULL, "usb_phy2_clk");
clk_enable(usb_clk);
usb_phy2_clk = usb_clk;
} else if (cpu_is_mx51()) {
usb_clk = clk_get(NULL, "usboh3_clk");
clk_enable(usb_clk);
usb_oh3_clk = usb_clk;
}
ret = fsl_usb_host_init(pdev);
if (ret)
return ret;
if (cpu_is_mx51()) {
/* setback USBH1_STP to be function */
#if 0 /* Jasper: Need to do... */
mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_SRE_FAST |
PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS |
PAD_CTL_DRV_VOT_LOW);
gpio_free(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP));
#endif
mxc_iomux_v3_setup_pad(usbh1stp_func);
gpio_free(MX5X_USBH1_STP);
}
/* disable remote wakeup irq */
USBCTRL &= ~UCTRL_H1WIE;
return 0;
}
static int fsl_usb_host_init_ext(struct platform_device *pdev)
{
int ret;
struct clk *usb_clk;
if (cpu_is_mx53()) {
usb_clk = clk_get(NULL, "usboh3_clk");
clk_enable(usb_clk);
clk_put(usb_clk);
usb_clk = clk_get(&pdev->dev, "usb_phy2_clk");
clk_enable(usb_clk);
clk_put(usb_clk);
/*derive clock from oscillator */
usb_clk = clk_get(NULL, "usb_utmi_clk");
clk_disable(usb_clk);
clk_put(usb_clk);
} else if (cpu_is_mx50()) {
usb_clk = clk_get(&pdev->dev, "usb_phy2_clk");
clk_enable(usb_clk);
clk_put(usb_clk);
}
ret = fsl_usb_host_init(pdev);
if (ret)
return ret;
if (cpu_is_mx51()) {
/* setback USBH1_STP to be function */
mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_SRE_FAST |
PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS |
PAD_CTL_DRV_VOT_LOW);
gpio_free(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP));
}
/* disable remote wakeup irq */
USBCTRL &= ~UCTRL_H1WIE;
return 0;
}
static int fsl_usb_host_init_ext(struct platform_device *pdev)
{
int ret;
struct clk *usb_clk;
usb_clk = clk_get(NULL, "usboh3_clk");
clk_enable(usb_clk);
usb_oh3_clk = usb_clk;
ret = fsl_usb_host_init(pdev);
if (ret) {
printk(KERN_ERR "host1 init fails......\n");
clk_disable(usb_oh3_clk);
clk_put(usb_oh3_clk);
return ret;
}
usbh1_internal_phy_clock_gate(true);
usb_phy_enable(pdev->dev.platform_data);
return 0;
}
static int fsl_usb_host_init_ext(struct platform_device *pdev)
{
int ret;
struct clk *usb_clk;
void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
usb_clk = clk_get(NULL, "usboh3_clk");
clk_enable(usb_clk);
usb_oh3_clk = usb_clk;
ret = fsl_usb_host_init(pdev);
if (ret) {
printk(KERN_ERR "host1 init fails......\n");
return ret;
}
usbh1_internal_phy_clock_gate(true);
usb_phy_enable(pdev->dev.platform_data);
usb_stop_mode_lock();
if (usb_stop_mode_refcount(true) == 1)
__raw_writel(BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG, anatop_base_addr + HW_ANADIG_ANA_MISC0_SET);
usb_stop_mode_unlock();
return 0;
}
static int fsl_usb_host_init_ext(struct platform_device *pdev)
{
int ret;
struct clk *usb_clk;
usb_clk = clk_get(NULL, "usboh3_clk");
clk_enable(usb_clk);
usb_oh3_clk = usb_clk;
usb_clk = clk_get(NULL, "usb_phy3_clk");
clk_enable(usb_clk);
usb_phy3_clk = usb_clk;
ret = fsl_usb_host_init(pdev);
if (ret) {
printk(KERN_ERR "host1 init fails......\n");
return ret;
}
usbh2_internal_phy_clock_gate(true);
/* Host2 HSIC enable */
USB_UH2_HSIC_CTRL |= HSIC_EN;
return 0;
}
