void bl2u_early_platform_setup(meminfo_t *mem_layout, void *plat_info) { arm_bl2u_early_platform_setup(mem_layout, plat_info); /* Initialize the platform config for future decision making */ fvp_config_setup(); }
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); /* Initialize the platform config for future decision making */ fvp_config_setup(); /* * Initialize the correct interconnect for this cluster during cold * boot. No need for locks as no other CPU is active. */ fvp_interconnect_init(); /* * Enable coherency in interconnect for the primary CPU's cluster. * Earlier bootloader stages might already do this (e.g. Trusted * Firmware's BL1 does it) but we can't assume so. There is no harm in * executing this code twice anyway. * FVP PSCI code will enable coherency for other clusters. */ fvp_interconnect_enable(); /* On FVP RevC, intialize SMMUv3 */ if (arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) smmuv3_init(PLAT_FVP_SMMUV3_BASE); }
/******************************************************************************* * Initialize the UART ******************************************************************************/ void tsp_early_platform_setup(void) { /* * Initialize a different console than already in use to display * messages from TSP */ console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE); /* Initialize the platform config for future decision making */ fvp_config_setup(); }
/******************************************************************************* * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 * in x0. This memory layout is sitting at the base of the free trusted SRAM. * Copy it to a safe loaction before its reclaimed by later BL2 functionality. ******************************************************************************/ void bl2_early_platform_setup(meminfo_t *mem_layout) { /* Initialize the console to provide early debug support */ console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); /* Setup the BL2 memory layout */ bl2_tzram_layout = *mem_layout; /* Initialize the platform config for future decision making */ fvp_config_setup(); /* Initialise the IO layer and register platform IO devices */ fvp_io_setup(); }
/******************************************************************************* * Perform any BL1 specific platform actions. ******************************************************************************/ void bl1_early_platform_setup(void) { arm_bl1_early_platform_setup(); /* Initialize the platform config for future decision making */ fvp_config_setup(); /* * Initialize CCI for this cluster during cold boot. * No need for locks as no other CPU is active. */ fvp_cci_init(); /* * Enable CCI coherency for the primary CPU's cluster. */ fvp_cci_enable(); }
void sp_min_early_platform_setup(void) { arm_sp_min_early_platform_setup(); /* Initialize the platform config for future decision making */ fvp_config_setup(); /* * Initialize the correct interconnect for this cluster during cold * boot. No need for locks as no other CPU is active. */ fvp_interconnect_init(); /* * Enable coherency in interconnect for the primary CPU's cluster. * Earlier bootloader stages might already do this (e.g. Trusted * Firmware's BL1 does it) but we can't assume so. There is no harm in * executing this code twice anyway. * FVP PSCI code will enable coherency for other clusters. */ fvp_interconnect_enable(); }