void TR_PPCOutOfLineCodeSection::generatePPCOutOfLineCodeSectionDispatch()
{
// Switch to cold helper instruction stream.
//
swapInstructionListsWithCompilation();
new (_cg->trHeapMemory()) TR::PPCLabelInstruction(TR::InstOpCode::label, _callNode, _entryLabel, _cg);
TR::Register *resultReg = NULL;
if (_callNode->getOpCode().isCallIndirect())
resultReg = TR::TreeEvaluator::performCall(_callNode, true, _cg);
else
resultReg = TR::TreeEvaluator::performCall(_callNode, false, _cg);
if (_targetReg)
{
TR_ASSERT(resultReg, "assertion failure");
generateTrg1Src1Instruction(_cg, TR::InstOpCode::mr, _callNode, _targetReg, resultReg);
}
_cg->decReferenceCount(_callNode);
if (_restartLabel)
generateLabelInstruction(_cg, TR::InstOpCode::b, _callNode, _restartLabel);
generateLabelInstruction(_cg, TR::InstOpCode::label, _callNode, TR::LabelSymbol::create(_cg->trHeapMemory(),_cg));
// Switch from cold helper instruction stream.
//
swapInstructionListsWithCompilation();
}
TR::Register *
TR::AMD64SystemLinkage::buildIndirectDispatch(TR::Node *callNode)
{
TR::SymbolReference *methodSymRef = callNode->getSymbolReference();
TR_ASSERT(methodSymRef->getSymbol()->castToMethodSymbol()->isComputed(), "system linkage only supports computed indirect call for now %p\n", callNode);
// Evaluate VFT
//
TR::Register *vftRegister;
TR::Node *vftNode = callNode->getFirstChild();
if (vftNode->getRegister())
{
vftRegister = vftNode->getRegister();
}
else
{
vftRegister = cg()->evaluate(vftNode);
}
// Allocate adequate register dependencies.
//
// pre = number of argument registers + 1 for VFT register
// post = number of volatile + VMThread + return register
//
uint32_t pre = getProperties().getNumIntegerArgumentRegisters() + getProperties().getNumFloatArgumentRegisters() + 1;
uint32_t post = getProperties().getNumVolatileRegisters() + 1 + (callNode->getDataType() == TR::NoType ? 0 : 1);
#if defined (PYTHON) && 0
// Treat all preserved GP regs as volatile until register map support available.
//
post += getProperties().getNumberOfPreservedGPRegisters();
#endif
TR::RegisterDependencyConditions *callDeps = generateRegisterDependencyConditions(pre, 1, cg());
TR::RealRegister::RegNum scratchRegIndex = getProperties().getIntegerScratchRegister(1);
callDeps->addPostCondition(vftRegister, scratchRegIndex, cg());
callDeps->stopAddingPostConditions();
// Evaluate outgoing arguments on the system stack and build pre-conditions.
//
int32_t memoryArgSize = buildArgs(callNode, callDeps);
// Dispatch
//
generateRegInstruction(CALLReg, callNode, vftRegister, callDeps, cg());
cg()->resetIsLeafMethod();
// Build label post-conditions
//
TR::RegisterDependencyConditions *postDeps = generateRegisterDependencyConditions(0, post, cg());
TR::Register *returnReg = buildVolatileAndReturnDependencies(callNode, postDeps);
postDeps->stopAddingPostConditions();
TR::LabelSymbol *postDepLabel = generateLabelSymbol(cg());
generateLabelInstruction(LABEL, callNode, postDepLabel, postDeps, cg());
return returnReg;
}
TR::Register *TR::IA32SystemLinkage::buildDirectDispatch(TR::Node *callNode, bool spillFPRegs)
{
TR::RealRegister *stackPointerReg = machine()->getX86RealRegister(TR::RealRegister::esp);
TR::SymbolReference *methodSymRef = callNode->getSymbolReference();
TR::MethodSymbol *methodSymbol = callNode->getSymbol()->castToMethodSymbol();
TR::ILOpCodes callOpCodeValue = callNode->getOpCodeValue();
if (!methodSymbol->isHelper())
diagnostic("Building call site for %s\n", methodSymbol->getMethod()->signature(trMemory()));
TR::RegisterDependencyConditions *deps;
deps = generateRegisterDependencyConditions((uint8_t)0, (uint8_t)6, cg());
TR::Register *returnReg = buildVolatileAndReturnDependencies(callNode, deps);
deps->stopAddingConditions();
TR::RegisterDependencyConditions *dummy = generateRegisterDependencyConditions((uint8_t)0, (uint8_t)0, cg());
uint32_t argSize = buildArgs(callNode, dummy);
TR::Register* targetAddressReg = NULL;
TR::MemoryReference* targetAddressMem = NULL;
// Call-out
int32_t stackAdjustment = cg()->getProperties().getCallerCleanup() ? 0 : -argSize;
TR::X86ImmInstruction* instr = generateImmSymInstruction(CALLImm4, callNode, (uintptr_t)methodSymbol->getMethodAddress(), methodSymRef, cg());
instr->setAdjustsFramePointerBy(stackAdjustment);
if (cg()->getProperties().getCallerCleanup() && argSize > 0)
{
// Clean up arguments
//
generateRegImmInstruction(
(argSize <= 127) ? ADD4RegImms : ADD4RegImm4,
callNode,
stackPointerReg,
argSize,
cg()
);
}
// Label denoting end of dispatch code sequence; dependencies are on
// this label rather than on the call
//
TR::LabelSymbol *endSystemCallSequence = generateLabelSymbol(cg());
generateLabelInstruction(LABEL, callNode, endSystemCallSequence, deps, cg());
// Stop using the killed registers that are not going to persist
//
if (deps)
stopUsingKilledRegisters(deps, returnReg);
// If the method returns a floating point value that is not used, insert a dummy store to
// eventually pop the value from the floating point stack.
//
if ((callNode->getDataType() == TR::Float ||
callNode->getDataType() == TR::Double) &&
callNode->getReferenceCount() == 1)
{
generateFPSTiST0RegRegInstruction(FSTRegReg, callNode, returnReg, returnReg, cg());
}
if (cg()->enableRegisterAssociations())
associatePreservedRegisters(deps, returnReg);
return returnReg;
}
TR::Register *OMR::X86::AMD64::TreeEvaluator::dbits2lEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
// TODO:AMD64: Peepholing
TR::Node *child = node->getFirstChild();
TR::Register *sreg = cg->evaluate(child);
TR::Register *treg = cg->allocateRegister(TR_GPR);
generateRegRegInstruction(MOVQReg8Reg, node, treg, sreg, cg);
if (node->normalizeNanValues())
{
static char *disableFastNormalizeNaNs = feGetEnv("TR_disableFastNormalizeNaNs");
if (disableFastNormalizeNaNs)
{
// This one is not clever, but it is simple, and it's based directly
// on the IA32 version which is known to work, so is safer.
//
TR::RegisterDependencyConditions *deps = generateRegisterDependencyConditions((uint8_t)0, (uint8_t)1, cg);
deps->addPostCondition(treg, TR::RealRegister::NoReg, cg);
TR::IA32ConstantDataSnippet *nan1Snippet = cg->findOrCreate8ByteConstant(node, DOUBLE_NAN_1_LOW);
TR::IA32ConstantDataSnippet *nan2Snippet = cg->findOrCreate8ByteConstant(node, DOUBLE_NAN_2_LOW);
TR::MemoryReference *nan1MR = generateX86MemoryReference(nan1Snippet, cg);
TR::MemoryReference *nan2MR = generateX86MemoryReference(nan2Snippet, cg);
TR::LabelSymbol *startLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
TR::LabelSymbol *normalizeLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
TR::LabelSymbol *endLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
startLabel->setStartInternalControlFlow();
endLabel ->setEndInternalControlFlow();
generateLabelInstruction( LABEL, node, startLabel, cg);
generateRegMemInstruction( CMP8RegMem, node, treg, nan1MR, cg);
generateLabelInstruction( JGE4, node, normalizeLabel, cg);
generateRegMemInstruction( CMP8RegMem, node, treg, nan2MR, cg);
generateLabelInstruction( JB4, node, endLabel, cg);
generateLabelInstruction( LABEL, node, normalizeLabel, cg);
generateRegImm64Instruction( MOV8RegImm64, node, treg, DOUBLE_NAN, cg);
generateLabelInstruction( LABEL, node, endLabel, deps, cg);
}
else
{
// A bunch of bookkeeping
//
uint64_t nanDetector = DOUBLE_NAN_2_LOW;
TR::RegisterDependencyConditions *internalControlFlowDeps = generateRegisterDependencyConditions((uint8_t)0, (uint8_t)1, cg);
internalControlFlowDeps->addPostCondition(treg, TR::RealRegister::NoReg, cg);
TR::RegisterDependencyConditions *helperDeps = generateRegisterDependencyConditions((uint8_t)1, (uint8_t)1, cg);
helperDeps->addPreCondition( treg, TR::RealRegister::eax, cg);
helperDeps->addPostCondition(treg, TR::RealRegister::eax, cg);
TR::IA32ConstantDataSnippet *nanDetectorSnippet = cg->findOrCreate8ByteConstant(node, nanDetector);
TR::MemoryReference *nanDetectorMR = generateX86MemoryReference(nanDetectorSnippet, cg);
TR::LabelSymbol *startLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
TR::LabelSymbol *slowPathLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
TR::LabelSymbol *normalizeLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
TR::LabelSymbol *endLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
startLabel->setStartInternalControlFlow();
endLabel ->setEndInternalControlFlow();
// Fast path: if subtracting nanDetector leaves CF=0 or OF=1, then it
// must be a NaN.
//
generateLabelInstruction( LABEL, node, startLabel, cg);
generateRegMemInstruction( CMP8RegMem, node, treg, nanDetectorMR, cg);
generateLabelInstruction( JAE4, node, slowPathLabel, cg);
generateLabelInstruction( JO4, node, slowPathLabel, cg);
// Slow path
//
TR_OutlinedInstructions *slowPath = new (cg->trHeapMemory()) TR_OutlinedInstructions(slowPathLabel, cg);
cg->getOutlinedInstructionsList().push_front(slowPath);
slowPath->swapInstructionListsWithCompilation();
generateLabelInstruction(NULL, LABEL, slowPathLabel, cg)->setNode(node);
generateRegImm64Instruction(MOV8RegImm64, node, treg, DOUBLE_NAN, cg);
generateLabelInstruction( JMP4, node, endLabel, cg);
slowPath->swapInstructionListsWithCompilation();
// Merge point
//
generateLabelInstruction(LABEL, node, endLabel, internalControlFlowDeps, cg);
}
}
node->setRegister(treg);
cg->decReferenceCount(child);
return treg;
}
TR::Register *TR::AMD64SystemLinkage::buildDirectDispatch(
TR::Node *callNode,
bool spillFPRegs)
{
TR::SymbolReference *methodSymRef = callNode->getSymbolReference();
TR::MethodSymbol *methodSymbol = methodSymRef->getSymbol()->castToMethodSymbol();
TR::Register *returnReg;
// Allocate adequate register dependencies.
//
// pre = number of argument registers
// post = number of volatile + return register
//
uint32_t pre = getProperties().getNumIntegerArgumentRegisters() + getProperties().getNumFloatArgumentRegisters();
uint32_t post = getProperties().getNumVolatileRegisters() + (callNode->getDataType() == TR::NoType ? 0 : 1);
#if defined (PYTHON) && 0
// Treat all preserved GP regs as volatile until register map support available.
//
post += getProperties().getNumberOfPreservedGPRegisters();
#endif
TR::RegisterDependencyConditions *preDeps = generateRegisterDependencyConditions(pre, 0, cg());
TR::RegisterDependencyConditions *postDeps = generateRegisterDependencyConditions(0, post, cg());
// Evaluate outgoing arguments on the system stack and build pre-conditions.
//
int32_t memoryArgSize = buildArgs(callNode, preDeps);
// Build post-conditions.
//
returnReg = buildVolatileAndReturnDependencies(callNode, postDeps);
postDeps->stopAddingPostConditions();
// Find the second scratch register in the post dependency list.
//
TR::Register *scratchReg = NULL;
TR::RealRegister::RegNum scratchRegIndex = getProperties().getIntegerScratchRegister(1);
for (int32_t i=0; i<post; i++)
{
if (postDeps->getPostConditions()->getRegisterDependency(i)->getRealRegister() == scratchRegIndex)
{
scratchReg = postDeps->getPostConditions()->getRegisterDependency(i)->getRegister();
break;
}
}
#if defined(PYTHON) && 0
// For Python, store the instruction that contains the GC map at this site into
// the frame object.
//
TR::SymbolReference *frameObjectSymRef =
comp()->getSymRefTab()->findOrCreateAutoSymbol(comp()->getMethodSymbol(), 0, TR::Address, true, false, true);
TR::Register *frameObjectRegister = cg()->allocateRegister();
generateRegMemInstruction(
L8RegMem,
callNode,
frameObjectRegister,
generateX86MemoryReference(frameObjectSymRef, cg()),
cg());
TR::RealRegister *espReal = cg()->machine()->getX86RealRegister(TR::RealRegister::esp);
TR::Register *gcMapPCRegister = cg()->allocateRegister();
generateRegMemInstruction(
LEA8RegMem,
callNode,
gcMapPCRegister,
generateX86MemoryReference(espReal, -8, cg()),
cg());
// Use "volatile" registers across the call. Once proper register map support
// is implemented, r14 and r15 will no longer be volatile and a different pair
// should be chosen.
//
TR::RegisterDependencyConditions *gcMapDeps = generateRegisterDependencyConditions(0, 2, cg());
gcMapDeps->addPostCondition(frameObjectRegister, TR::RealRegister::r14, cg());
gcMapDeps->addPostCondition(gcMapPCRegister, TR::RealRegister::r15, cg());
gcMapDeps->stopAddingPostConditions();
generateMemRegInstruction(
S8MemReg,
callNode,
generateX86MemoryReference(frameObjectRegister, fe()->getPythonGCMapPCOffsetInFrame(), cg()),
gcMapPCRegister,
gcMapDeps,
cg());
cg()->stopUsingRegister(frameObjectRegister);
cg()->stopUsingRegister(gcMapPCRegister);
#endif
TR::Instruction *instr;
if (methodSymbol->getMethodAddress())
{
TR_ASSERT(scratchReg, "could not find second scratch register");
auto LoadRegisterInstruction = generateRegImm64SymInstruction(
MOV8RegImm64,
callNode,
scratchReg,
(uintptr_t)methodSymbol->getMethodAddress(),
methodSymRef,
cg());
if (TR::Options::getCmdLineOptions()->getOption(TR_EmitRelocatableELFFile))
{
LoadRegisterInstruction->setReloKind(TR_NativeMethodAbsolute);
}
instr = generateRegInstruction(CALLReg, callNode, scratchReg, preDeps, cg());
}
else
{
instr = generateImmSymInstruction(CALLImm4, callNode, (uintptrj_t)methodSymbol->getMethodAddress(), methodSymRef, preDeps, cg());
}
cg()->resetIsLeafMethod();
instr->setNeedsGCMap(getProperties().getPreservedRegisterMapForGC());
cg()->stopUsingRegister(scratchReg);
TR::LabelSymbol *postDepLabel = generateLabelSymbol(cg());
generateLabelInstruction(LABEL, callNode, postDepLabel, postDeps, cg());
return returnReg;
}
TR::Register *TR::AMD64SystemLinkage::buildDirectDispatch(
TR::Node *callNode,
bool spillFPRegs)
{
TR::SymbolReference *methodSymRef = callNode->getSymbolReference();
TR::MethodSymbol *methodSymbol = methodSymRef->getSymbol()->castToMethodSymbol();
TR::Register *returnReg;
// Allocate adequate register dependencies.
//
// pre = number of argument registers
// post = number of volatile + return register
//
uint32_t pre = getProperties().getNumIntegerArgumentRegisters() + getProperties().getNumFloatArgumentRegisters();
uint32_t post = getProperties().getNumVolatileRegisters() + (callNode->getDataType() == TR::NoType ? 0 : 1);
TR::RegisterDependencyConditions *preDeps = generateRegisterDependencyConditions(pre, 0, cg());
TR::RegisterDependencyConditions *postDeps = generateRegisterDependencyConditions(0, post, cg());
// Evaluate outgoing arguments on the system stack and build pre-conditions.
//
int32_t memoryArgSize = buildArgs(callNode, preDeps);
// Build post-conditions.
//
returnReg = buildVolatileAndReturnDependencies(callNode, postDeps);
postDeps->stopAddingPostConditions();
// Find the second scratch register in the post dependency list.
//
TR::Register *scratchReg = NULL;
TR::RealRegister::RegNum scratchRegIndex = getProperties().getIntegerScratchRegister(1);
for (int32_t i=0; i<post; i++)
{
if (postDeps->getPostConditions()->getRegisterDependency(i)->getRealRegister() == scratchRegIndex)
{
scratchReg = postDeps->getPostConditions()->getRegisterDependency(i)->getRegister();
break;
}
}
TR::Instruction *instr;
if (methodSymbol->getMethodAddress())
{
TR_ASSERT(scratchReg, "could not find second scratch register");
auto LoadRegisterInstruction = generateRegImm64SymInstruction(
MOV8RegImm64,
callNode,
scratchReg,
(uintptr_t)methodSymbol->getMethodAddress(),
methodSymRef,
cg());
if (comp()->getOption(TR_EmitRelocatableELFFile))
{
LoadRegisterInstruction->setReloKind(TR_NativeMethodAbsolute);
}
instr = generateRegInstruction(CALLReg, callNode, scratchReg, preDeps, cg());
}
else
{
instr = generateImmSymInstruction(CALLImm4, callNode, (uintptrj_t)methodSymbol->getMethodAddress(), methodSymRef, preDeps, cg());
}
cg()->resetIsLeafMethod();
instr->setNeedsGCMap(getProperties().getPreservedRegisterMapForGC());
cg()->stopUsingRegister(scratchReg);
TR::LabelSymbol *postDepLabel = generateLabelSymbol(cg());
generateLabelInstruction(LABEL, callNode, postDepLabel, postDeps, cg());
return returnReg;
}
void TR_OutlinedInstructions::generateOutlinedInstructionsDispatch()
{
// Switch to cold helper instruction stream.
//
TR::Register *vmThreadReg = _cg->getMethodMetaDataRegister();
TR::Instruction *savedFirstInstruction = comp()->getFirstInstruction();
TR::Instruction *savedAppendInstruction = comp()->getAppendInstruction();
comp()->setFirstInstruction(NULL);
comp()->setAppendInstruction(NULL);
new (_cg->trHeapMemory()) TR::X86LabelInstruction(NULL, LABEL, _entryLabel, _cg);
if (_rematerializeVMThread)
{
generateRegInstruction(PUSHReg, _callNode, vmThreadReg, _cg);
generateRestoreVMThreadInstruction ( _callNode, _cg);
TR::MemoryReference *vmThreadMR = generateX86MemoryReference(vmThreadReg, (TR::Compiler->target.is64Bit()) ? 16 : 8, _cg);
generateRegMemInstruction (LRegMem(), _callNode, vmThreadReg, vmThreadMR, _cg);
}
TR::Register *resultReg=NULL;
if (_callNode->getOpCode().isCallIndirect())
resultReg = TR::TreeEvaluator::performCall(_callNode, true, false, _cg);
else
resultReg = TR::TreeEvaluator::performCall(_callNode, false, false, _cg);
if (_rematerializeVMThread)
{
generateRegInstruction(POPReg, _callNode, vmThreadReg, _cg);
}
if (_targetReg)
{
TR_ASSERT(resultReg, "assertion failure");
TR::RegisterPair *targetRegPair = _targetReg->getRegisterPair();
TR::RegisterPair *resultRegPair = resultReg->getRegisterPair();
if (targetRegPair)
{
TR_ASSERT(resultRegPair, "OutlinedInstructions: targetReg is a register pair and resultReg is not");
generateRegRegInstruction(_targetRegMovOpcode, _callNode, targetRegPair->getLowOrder(), resultRegPair->getLowOrder(), _cg);
generateRegRegInstruction(_targetRegMovOpcode, _callNode, targetRegPair->getHighOrder(), resultRegPair->getHighOrder(), _cg);
}
else
{
TR_ASSERT(!resultRegPair, "OutlinedInstructions: resultReg is a register pair and targetReg is not");
generateRegRegInstruction(_targetRegMovOpcode, _callNode, _targetReg, resultReg, _cg);
}
}
_cg->decReferenceCount(_callNode);
if (_restartLabel)
generateLabelInstruction(JMP4, _callNode, _restartLabel, _cg);
else
{
// Java-specific.
// No restart label implies we're not coming back from this call,
// so it's safe to put data after the call. In the case of calling a throw
// helper, there's an ancient busted handshake that expects to find a 4-byte
// offset here, so we have to comply...
//
// When the handshake is removed, we can delete this zero.
//
generateImmInstruction(DDImm4, _callNode, 0, _cg);
}
// Dummy label to delimit the end of the helper call dispatch sequence (for exception ranges).
//
generateLabelInstruction(LABEL, _callNode, TR::LabelSymbol::create(_cg->trHeapMemory(),_cg), _cg);
// Switch from cold helper instruction stream.
//
_firstInstruction = comp()->getFirstInstruction();
_appendInstruction = comp()->getAppendInstruction();
comp()->setFirstInstruction(savedFirstInstruction);
comp()->setAppendInstruction(savedAppendInstruction);
}
