int __init generic_timer_clocksource_init(void)
{
int rc;
struct vmm_clocksource *cs;
struct vmm_devtree_node *node;
node = vmm_devtree_find_matching(NULL, generic_timer_match);
if (!node) {
return VMM_ENODEV;
}
if (generic_timer_hz == 0) {
rc = vmm_devtree_clock_frequency(node, &generic_timer_hz);
if (rc) {
/* Use preconfigured counter frequency
* in absence of dts node
*/
generic_timer_hz =
generic_timer_reg_read(GENERIC_TIMER_REG_FREQ);
} else {
if (generic_timer_freq_writeable()) {
/* Program the counter frequency
* as per the dts node
*/
generic_timer_reg_write(GENERIC_TIMER_REG_FREQ,
generic_timer_hz);
}
}
}
if (generic_timer_hz == 0) {
return VMM_EFAIL;
}
cs = vmm_zalloc(sizeof(struct vmm_clocksource));
if (!cs) {
return VMM_EFAIL;
}
cs->name = "gen-timer";
cs->rating = 400;
cs->read = &generic_counter_read;
cs->mask = VMM_CLOCKSOURCE_MASK(56);
vmm_clocks_calc_mult_shift(&cs->mult, &cs->shift,
generic_timer_hz, VMM_NSEC_PER_SEC, 10);
cs->priv = NULL;
return vmm_clocksource_register(cs);
}
static void generic_timer_get_freq(struct vmm_devtree_node *node)
{
int rc;
if (generic_timer_hz == 0) {
rc = vmm_devtree_clock_frequency(node, &generic_timer_hz);
if (rc) {
/* Use preconfigured counter frequency
* in absence of dts node
*/
generic_timer_hz =
generic_timer_reg_read(GENERIC_TIMER_REG_FREQ);
} else {
if (generic_timer_freq_writeable()) {
/* Program the counter frequency
* as per the dts node
*/
generic_timer_reg_write(GENERIC_TIMER_REG_FREQ,
generic_timer_hz);
}
}
}
}
int __cpuinit generic_timer_clockchip_init(void)
{
int rc;
u32 irq[3], num_irqs, val;
struct vmm_clockchip *cc;
struct vmm_devtree_node *node;
/* Find generic timer device tree node */
node = vmm_devtree_find_matching(NULL, generic_timer_match);
if (!node) {
return VMM_ENODEV;
}
/* Determine generic timer frequency */
if (generic_timer_hz == 0) {
rc = vmm_devtree_clock_frequency(node, &generic_timer_hz);
if (rc) {
/* Use preconfigured counter frequency
* in absence of dts node
*/
generic_timer_hz =
generic_timer_reg_read(GENERIC_TIMER_REG_FREQ);
} else if (generic_timer_freq_writeable()) {
/* Program the counter frequency as per the dts node */
generic_timer_reg_write(GENERIC_TIMER_REG_FREQ,
generic_timer_hz);
}
}
if (generic_timer_hz == 0) {
return VMM_EFAIL;
}
/* Get hypervisor timer irq number */
rc = vmm_devtree_irq_get(node,
&irq[GENERIC_HYPERVISOR_TIMER],
GENERIC_HYPERVISOR_TIMER);
if (rc) {
return rc;
}
/* Get physical timer irq number */
rc = vmm_devtree_irq_get(node,
&irq[GENERIC_PHYSICAL_TIMER],
GENERIC_PHYSICAL_TIMER);
if (rc) {
return rc;
}
/* Get virtual timer irq number */
rc = vmm_devtree_irq_get(node,
&irq[GENERIC_VIRTUAL_TIMER],
GENERIC_VIRTUAL_TIMER);
if (rc) {
return rc;
}
/* Number of generic timer irqs */
num_irqs = vmm_devtree_irq_count(node);
if (!num_irqs) {
return VMM_EFAIL;
}
/* Ensure hypervisor timer is stopped */
generic_timer_stop();
/* Create generic hypervisor timer clockchip */
cc = vmm_zalloc(sizeof(struct vmm_clockchip));
if (!cc) {
return VMM_EFAIL;
}
cc->name = "gen-hyp-timer";
cc->hirq = irq[GENERIC_HYPERVISOR_TIMER];
cc->rating = 400;
cc->cpumask = vmm_cpumask_of(vmm_smp_processor_id());
cc->features = VMM_CLOCKCHIP_FEAT_ONESHOT;
vmm_clocks_calc_mult_shift(&cc->mult, &cc->shift,
VMM_NSEC_PER_SEC, generic_timer_hz, 10);
cc->min_delta_ns = vmm_clockchip_delta2ns(0xF, cc);
cc->max_delta_ns = vmm_clockchip_delta2ns(0x7FFFFFFF, cc);
cc->set_mode = &generic_timer_set_mode;
cc->set_next_event = &generic_timer_set_next_event;
cc->priv = NULL;
/* Register hypervisor timer clockchip */
rc = vmm_clockchip_register(cc);
if (rc) {
goto fail_free_cc;
}
if (!vmm_smp_processor_id()) {
/* Register irq handler for hypervisor timer */
rc = vmm_host_irq_register(irq[GENERIC_HYPERVISOR_TIMER],
"gen-hyp-timer",
&generic_hyp_timer_handler, cc);
if (rc) {
goto fail_unreg_cc;
}
/* Mark hypervisor timer irq as per-CPU */
if ((rc = vmm_host_irq_mark_per_cpu(cc->hirq))) {
goto fail_unreg_htimer;
}
if (num_irqs > 1) {
/* Register irq handler for physical timer */
rc = vmm_host_irq_register(irq[GENERIC_PHYSICAL_TIMER],
"gen-phys-timer",
&generic_phys_timer_handler,
NULL);
if (rc) {
goto fail_unreg_htimer;
}
/* Mark physical timer irq as per-CPU */
rc = vmm_host_irq_mark_per_cpu(
irq[GENERIC_PHYSICAL_TIMER]);
if (rc) {
goto fail_unreg_ptimer;
}
}
if (num_irqs > 2) {
/* Register irq handler for virtual timer */
rc = vmm_host_irq_register(irq[GENERIC_VIRTUAL_TIMER],
"gen-virt-timer",
&generic_virt_timer_handler,
NULL);
if (rc) {
goto fail_unreg_ptimer;
}
/* Mark virtual timer irq as per-CPU */
rc = vmm_host_irq_mark_per_cpu(
irq[GENERIC_VIRTUAL_TIMER]);
if (rc) {
goto fail_unreg_vtimer;
}
}
}
if (num_irqs > 1) {
val = generic_timer_reg_read(GENERIC_TIMER_REG_HCTL);
val |= GENERIC_TIMER_HCTL_KERN_PCNT_EN;
val |= GENERIC_TIMER_HCTL_KERN_PTMR_EN;
generic_timer_reg_write(GENERIC_TIMER_REG_HCTL, val);
}
for (val = 0; val < num_irqs; val++) {
gic_enable_ppi(irq[val]);
}
return VMM_OK;
fail_unreg_vtimer:
if (!vmm_smp_processor_id() && num_irqs > 2) {
vmm_host_irq_unregister(irq[GENERIC_HYPERVISOR_TIMER],
&generic_virt_timer_handler);
}
fail_unreg_ptimer:
if (!vmm_smp_processor_id() && num_irqs > 1) {
vmm_host_irq_unregister(irq[GENERIC_PHYSICAL_TIMER],
&generic_phys_timer_handler);
}
fail_unreg_htimer:
if (!vmm_smp_processor_id()) {
vmm_host_irq_unregister(irq[GENERIC_HYPERVISOR_TIMER],
&generic_hyp_timer_handler);
}
fail_unreg_cc:
vmm_clockchip_register(cc);
fail_free_cc:
vmm_free(cc);
return rc;
}
