static void setup_audio_wall_dto(
const struct hw_ctx_audio *hw_ctx,
enum signal_type signal,
const struct audio_crtc_info *crtc_info,
const struct audio_pll_info *pll_info)
{
struct azalia_clock_info clock_info = { 0 };
uint32_t value = dal_read_reg(hw_ctx->ctx, mmDCCG_AUDIO_DTO_SOURCE);
/* TODO: GraphicsObject\inc\GraphicsObjectDefs.hpp(131):
*inline bool isHdmiSignal(SignalType signal)
*if (Signals::isHdmiSignal(signal))
*/
if (dal_is_hdmi_signal(signal)) {
/*DTO0 Programming goal:
-generate 24MHz, 128*Fs from 24MHz
-use DTO0 when an active HDMI port is connected
(optionally a DP is connected) */
/* calculate DTO settings */
get_azalia_clock_info_hdmi(
hw_ctx,
crtc_info->requested_pixel_clock,
crtc_info->calculated_pixel_clock,
&clock_info);
/* On TN/SI, Program DTO source select and DTO select before
programming DTO modulo and DTO phase. These bits must be
programmed first, otherwise there will be no HDMI audio at boot
up. This is a HW sequence change (different from old ASICs).
Caution when changing this programming sequence.
HDMI enabled, using DTO0
program master CRTC for DTO0 */
{
set_reg_field_value(value,
pll_info->dto_source - DTO_SOURCE_ID0,
DCCG_AUDIO_DTO_SOURCE,
DCCG_AUDIO_DTO0_SOURCE_SEL);
set_reg_field_value(value,
0,
DCCG_AUDIO_DTO_SOURCE,
DCCG_AUDIO_DTO_SEL);
dal_write_reg(hw_ctx->ctx,
mmDCCG_AUDIO_DTO_SOURCE, value);
}
/* module */
{
value = dal_read_reg(hw_ctx->ctx,
mmDCCG_AUDIO_DTO0_MODULE);
set_reg_field_value(value,
clock_info.audio_dto_module,
DCCG_AUDIO_DTO0_MODULE,
DCCG_AUDIO_DTO0_MODULE);
dal_write_reg(hw_ctx->ctx,
mmDCCG_AUDIO_DTO0_MODULE, value);
}
/* phase */
{
value = 0;
value = dal_read_reg(hw_ctx->ctx,
mmDCCG_AUDIO_DTO0_PHASE);
set_reg_field_value(value,
clock_info.audio_dto_phase,
DCCG_AUDIO_DTO0_PHASE,
DCCG_AUDIO_DTO0_PHASE);
dal_write_reg(hw_ctx->ctx,
mmDCCG_AUDIO_DTO0_PHASE, value);
}
} else {
/*DTO1 Programming goal:
-generate 24MHz, 512*Fs, 128*Fs from 24MHz
-default is to used DTO1, and switch to DTO0 when an audio
master HDMI port is connected
-use as default for DP
calculate DTO settings */
get_azalia_clock_info_dp(
hw_ctx,
crtc_info->requested_pixel_clock,
pll_info,
&clock_info);
/* Program DTO select before programming DTO modulo and DTO
phase. default to use DTO1 */
{
set_reg_field_value(value, 1,
DCCG_AUDIO_DTO_SOURCE,
DCCG_AUDIO_DTO_SEL);
/*dal_write_reg(mmDCCG_AUDIO_DTO_SOURCE, value)*/
/* Select 512fs for DP TODO: web register definition
does not match register header file
set_reg_field_value(value, 1,
DCCG_AUDIO_DTO_SOURCE,
DCCG_AUDIO_DTO2_USE_512FBR_DTO);
*/
dal_write_reg(hw_ctx->ctx,
mmDCCG_AUDIO_DTO_SOURCE, value);
}
/* module */
{
value = 0;
value = dal_read_reg(hw_ctx->ctx,
mmDCCG_AUDIO_DTO1_MODULE);
set_reg_field_value(value,
clock_info.audio_dto_module,
DCCG_AUDIO_DTO1_MODULE,
DCCG_AUDIO_DTO1_MODULE);
dal_write_reg(hw_ctx->ctx,
mmDCCG_AUDIO_DTO1_MODULE, value);
}
/* phase */
{
value = 0;
value = dal_read_reg(hw_ctx->ctx,
mmDCCG_AUDIO_DTO1_PHASE);
set_reg_field_value(value,
clock_info.audio_dto_phase,
DCCG_AUDIO_DTO1_PHASE,
DCCG_AUDIO_DTO1_PHASE);
dal_write_reg(hw_ctx->ctx,
mmDCCG_AUDIO_DTO1_PHASE, value);
}
/* DAL2 code separate DCCG_AUDIO_DTO_SEL and
DCCG_AUDIO_DTO2_USE_512FBR_DTO programming into two different
location. merge together should not hurt */
/*value.bits.DCCG_AUDIO_DTO2_USE_512FBR_DTO = 1;
dal_write_reg(mmDCCG_AUDIO_DTO_SOURCE, value);*/
}
}
void dce_aud_wall_dto_setup(
struct audio *audio,
enum signal_type signal,
const struct audio_crtc_info *crtc_info,
const struct audio_pll_info *pll_info)
{
struct dce_audio *aud = DCE_AUD(audio);
struct azalia_clock_info clock_info = { 0 };
if (dc_is_hdmi_signal(signal)) {
uint32_t src_sel;
/*DTO0 Programming goal:
-generate 24MHz, 128*Fs from 24MHz
-use DTO0 when an active HDMI port is connected
(optionally a DP is connected) */
/* calculate DTO settings */
get_azalia_clock_info_hdmi(
crtc_info->requested_pixel_clock,
crtc_info->calculated_pixel_clock,
&clock_info);
DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock = %d"\
"calculated_pixel_clock =%d\n"\
"audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
crtc_info->requested_pixel_clock,\
crtc_info->calculated_pixel_clock,\
clock_info.audio_dto_module,\
clock_info.audio_dto_phase);
/* On TN/SI, Program DTO source select and DTO select before
programming DTO modulo and DTO phase. These bits must be
programmed first, otherwise there will be no HDMI audio at boot
up. This is a HW sequence change (different from old ASICs).
Caution when changing this programming sequence.
HDMI enabled, using DTO0
program master CRTC for DTO0 */
src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE,
DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel,
DCCG_AUDIO_DTO_SEL, 0);
/* module */
REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,
DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module);
/* phase */
REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,
DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase);
} else {
/*DTO1 Programming goal:
-generate 24MHz, 512*Fs, 128*Fs from 24MHz
-default is to used DTO1, and switch to DTO0 when an audio
master HDMI port is connected
-use as default for DP
calculate DTO settings */
get_azalia_clock_info_dp(
crtc_info->requested_pixel_clock,
pll_info,
&clock_info);
/* Program DTO select before programming DTO modulo and DTO
phase. default to use DTO1 */
REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
DCCG_AUDIO_DTO_SEL, 1);
REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
DCCG_AUDIO_DTO_SEL, 1);
/* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1)
* Select 512fs for DP TODO: web register definition
* does not match register header file
* DCE11 version it's commented out while DCE8 it's set to 1
*/
/* module */
REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,
DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module);
/* phase */
REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,
DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase);
REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1);
}
}
