static int __init get_core_nominal_mv_index(int speedo_id)
{
int i;
int mv = tegra_core_speedo_mv();
#if 0 /* fixme: hard code to let CPU voltage can be no limited */
int core_edp_limit = get_core_edp();
#else
int core_edp_limit = 0;
#endif
/*
* Start with nominal level for the chips with this speedo_id. Then,
* make sure core nominal voltage is below edp limit for the board
* (if edp limit is set).
*/
if (core_edp_limit)
mv = min(mv, core_edp_limit);
pr_info("core voltage => %i\n", mv);
/* Round nominal level down to the nearest core scaling step */
for (i = 0; i < MAX_DVFS_FREQS; i++) {
if ((core_millivolts[i] == 0) || (mv < core_millivolts[i]))
break;
}
pr_info("core_nominal_mv_index: %i\n", (i-1));
if (i == 0) {
pr_err("tegra3_dvfs: unable to adjust core dvfs table to"
" nominal voltage %d\n", mv);
return -ENOSYS;
}
return (i - 1);
}
static int __init get_core_nominal_mv_index(int speedo_id)
{
int i, mv;
int core_edp_limit = get_core_edp();
/*
* Start with nominal level for the chips with this speedo_id. Then,
* make sure core nominal voltage is below edp limit for the board
* (if edp limit is set).
*/
BUG_ON(speedo_id >= ARRAY_SIZE(core_speedo_nominal_millivolts));
mv = core_speedo_nominal_millivolts[speedo_id];
if (core_edp_limit)
mv = min(mv, core_edp_limit);
/* Round nominal level down to the nearest core scaling step */
for (i = 0; i < MAX_DVFS_FREQS; i++) {
if ((core_millivolts[i] == 0) || (mv < core_millivolts[i]))
break;
}
if (i == 0) {
pr_err("tegra3_dvfs: unable to adjust core dvfs table to"
" nominal voltage %d\n", mv);
return -ENOSYS;
}
return (i - 1);
}
