static void set_memory_clock(unsigned int frequency)
{
unsigned int reg, divisor;
/*
* Cheok_0509: For SM750LE, the memory clock is fixed.
* Nothing to set.
*/
if (sm750_get_chip_type() == SM750LE)
return;
if (frequency) {
/*
* Set the frequency to the maximum frequency
* that the DDR Memory can take which is 336MHz.
*/
if (frequency > MHz(336))
frequency = MHz(336);
/* Calculate the divisor */
divisor = DIV_ROUND_CLOSEST(get_mxclk_freq(), frequency);
/* Set the corresponding divisor in the register. */
reg = peek32(CURRENT_GATE) & ~CURRENT_GATE_M2XCLK_MASK;
switch (divisor) {
default:
case 1:
reg |= CURRENT_GATE_M2XCLK_DIV_1;
break;
case 2:
reg |= CURRENT_GATE_M2XCLK_DIV_2;
break;
case 3:
reg |= CURRENT_GATE_M2XCLK_DIV_3;
break;
case 4:
reg |= CURRENT_GATE_M2XCLK_DIV_4;
break;
}
sm750_set_current_gate(reg);
}
}
static void setMemoryClock(unsigned int frequency)
{
unsigned int reg, divisor;
/* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */
if (getChipType() == SM750LE)
return;
if (frequency) {
/* Set the frequency to the maximum frequency that the DDR Memory can take
which is 336MHz. */
if (frequency > MHz(336))
frequency = MHz(336);
/* Calculate the divisor */
divisor = roundedDiv(get_mxclk_freq(), frequency);
/* Set the corresponding divisor in the register. */
reg = PEEK32(CURRENT_GATE) & ~CURRENT_GATE_M2XCLK_MASK;
switch (divisor) {
default:
case 1:
reg |= CURRENT_GATE_M2XCLK_DIV_1;
break;
case 2:
reg |= CURRENT_GATE_M2XCLK_DIV_2;
break;
case 3:
reg |= CURRENT_GATE_M2XCLK_DIV_3;
break;
case 4:
reg |= CURRENT_GATE_M2XCLK_DIV_4;
break;
}
setCurrentGate(reg);
}
}
/*
* This function set up the master clock (MCLK).
*
* Input: Frequency to be set.
*
* NOTE:
* The maximum frequency the engine can run is 168MHz.
*/
static void setMasterClock(unsigned int frequency)
{
unsigned int reg, divisor;
/* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */
if (getChipType() == SM750LE)
return;
if (frequency) {
/* Set the frequency to the maximum frequency that the SM750 engine can
run, which is about 190 MHz. */
if (frequency > MHz(190))
frequency = MHz(190);
/* Calculate the divisor */
divisor = roundedDiv(get_mxclk_freq(), frequency);
/* Set the corresponding divisor in the register. */
reg = PEEK32(CURRENT_GATE) & ~CURRENT_GATE_MCLK_MASK;
switch (divisor) {
default:
case 3:
reg |= CURRENT_GATE_MCLK_DIV_3;
break;
case 4:
reg |= CURRENT_GATE_MCLK_DIV_4;
break;
case 6:
reg |= CURRENT_GATE_MCLK_DIV_6;
break;
case 8:
reg |= CURRENT_GATE_MCLK_DIV_8;
break;
}
setCurrentGate(reg);
}
}
