void bl(int i) { /* I1 = NOT(J1 EOR S); I2 = NOT(J2 EOR S); imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); if InITBlock() && !LastInITBlock() then UNPREDICTABLE; if ConditionPassed() then EncodingSpecificOperations(); next_instr_addr = PC; LR = next_instr_addr<31:1> : '1'; SelectInstrSet(InstrSet_Thumb); BranchWritePC(PC + imm32); */ int i1,i2,imm32,next_instr_addr; *((int *)(&branchWithLink)) = i; i1=!(branchWithLink.j1^branchWithLink.s); i2=!(branchWithLink.j2^branchWithLink.s); imm32=(branchWithLink.s<<24)|(i1<<23)|(i2<<22)|(branchWithLink.off2<<12)|(branchWithLink.off1<<1); imm32 &= 0xFFFFFFFE; //SignExtend if(imm32 & 0x01000000) imm32 |= 0xFE000000; else imm32 &= 0x01FFFFFF; if(InITBlock() && !LastInITBlock()) printf("UNPREDICTABLE instruction.\n"); else{ EncodingSpecificOperations(); next_instr_addr=get_pc(); set_lr(next_instr_addr | 0x00000001); //SelectInstrSet(InstrSet_Thumb); questionhi BranchWritePC(get_pc()+imm32); } }
static int inline running_in_sram(void) { u32 addr = get_pc(); addr >>= 28; return addr == 0; }
void process::cont() { switch(get_last_event()) { case EV_TRACING: { uintptr_t pc = get_pc() - BREAKPOINT_INSN_LEN; cont_from_bp(pc); adjust_call_stack_post(pc); } return; case EV_SIGSTOP: case EV_FORK: case EV_CLONE: case EV_EXEC: case EV_NEW: case EV_UNKNOWN: tracer_.cont(); return; case EV_SIGNALED: case EV_SIGNALED_CRITICAL: tracer_.send_signal(get_last_signal()); // and cont return; case EV_EXIT: case EV_SIG_EXIT: break; } assert(false); }
int main() { int itr; int nCount; /* 문제의 테스트 케이스 */ int n, r; int p, q; //p순열 q조합 int p_pcnt, p_qcnt; char str[15]; char qarr[111][111]; scanf("%d", &nCount); /* 테스트 케이스 입력 */ for(itr=0; itr<nCount; itr++) { p_pcnt = 0; p_qcnt = 0; for(int i=0; i<111; i++) { for(int j=0; j<111; j++) { qarr[i][j] = -1; } } printf("#testcase%d\n",itr+1); scanf("%d %d", &n, &r); scanf("%d %d", &p, &q); get_pc(0, n, r, str, &p_pcnt, &p_qcnt, p, q, qarr); } return 0; /* 반드시 return 0으로 해주셔야합니다. */ }
void b_t4(int i) { /* I1 = NOT(J1 EOR S); I2 = NOT(J2 EOR S); imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); if InITBlock() && !LastInITBlock() then UNPREDICTABLE; if ConditionPassed() then EncodingSpecificOperations(); BranchWritePC(PC + imm32); */ int imm32,i1,i2; *((int *)(&branch)) = i; i1=!(branch.j1^branch.s); i2=!(branch.j2^branch.s); imm32=(branch.s<<24)|(i1<<23)+(i2<<22)|(branch.off2<<12)|(branch.off1<<1); imm32 &= 0xFFFFFFFE; //SignExtend if(imm32 & 0x01000000) imm32 |= 0xFE000000; else imm32 &= 0x01FFFFFF; if(InITBlock() && !LastInITBlock()) printf("UNPREDICTABLE instruction.\n"); else{ EncodingSpecificOperations(); BranchWritePC(get_pc()+imm32); } }
int execute_instruction(MIPS simulateur, BP * breakpoint, INSTR * instruction_asm, char * error){ unsigned int PC; int right; uint instruction; uint opcode; uint rs; uint rt; uint rd; uint sa; uint function; uint immediate; uint instr_index; uint reste; PC = get_pc(simulateur); instruction = assemble_mot(get_mem(simulateur, PC), get_mem(simulateur, PC+1), get_mem(simulateur, PC+2), get_mem(simulateur, PC+3)); if(PC < file_sim->text || PC > file_sim->text + file_sim->sizetext){ sprintf(error, " ERROR. Execution forbiden outside of the section .text"); return 2; } PC = PC+4; if(set_pc(simulateur, PC) == 2){ RED printf("\n execution Adress uncorrect\n"); ENDCOLOR return 1; }
static noinline __noreturn void tqmls1046a_r_entry(unsigned long memsize) { unsigned long membase = LS1046A_DDR_SDRAM_BASE; if (get_pc() >= membase) { if (memsize + membase >= 0x100000000) memsize = 0x100000000 - membase; barebox_arm_entry(membase, 0x80000000, __dtb_fsl_tqmls1046a_mbls10xxa_start); } arm_cpu_lowlevel_init(); debug_ll_init(); ls1046a_init_lowlevel(); memsize = fsl_ddr_sdram(&ls1046a_info); ls1046a_errata_post_ddr(); ls1046a_esdhc_start_image(memsize, 0, 0); pr_err("Booting failed\n"); while (1); }
void initdram (int board_type) { ulong dramsize = 0; ulong test1, test2; /* Setup pin multiplexing */ /* PSC6=UART, PSC3=UART ; Ether=100MBit with MD */ *(vu_long *)MPC5XXX_GPS_PORT_CONFIG = 0x00559c10; *(vu_long *)MPC5XXX_CS_BURST = 0x00000000; *(vu_long *)MPC5XXX_CS_DEADCYCLE = 0x33333333; /* * Make USB work due to the special base crystal frequency: * 33,3330MHz * 16 = 533,328MHz main clock, but should be 528 MHz Clock */ out_be32((void *)MPC5XXX_CDM_48_FDC, 0x00015555); mpc5200_setup_bus_clocks(1, 4); if (get_pc() > SZ_128M) { /* setup SDRAM chip selects */ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001b;/* 256MB at 0x0 */ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x10000000;/* disabled */ __asm__ volatile ("sync"); /* setup config registers */ *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; __asm__ volatile ("sync"); #if SDRAM_DDR && SDRAM_TAPDELAY /* set tap delay */ *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; __asm__ volatile ("sync"); #endif /* find RAM size using SDRAM CS0 only */ sdram_start(0); test1 = get_ram_size((ulong *)0, 0x10000000); sdram_start(1); test2 = get_ram_size((ulong *)0, 0x10000000); if (test1 > test2) { sdram_start(0); dramsize = test1; } else { dramsize = test2; } /* memory smaller than 1MB is impossible */ if (dramsize < (1 << 20)) { dramsize = 0; } /* set SDRAM CS0 size according to the amount of RAM found */ if (dramsize > 0) { *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; } else {
static void power4_handle_interrupt(struct pt_regs *regs, struct op_counter_config *ctr) { unsigned long pc; int is_kernel; int val; int i; unsigned int mmcr0; unsigned long mmcra; mmcra = mfspr(SPRN_MMCRA); pc = get_pc(regs); is_kernel = get_kernel(pc, mmcra); /* set the PMM bit (see comment below) */ mtmsrd(mfmsr() | MSR_PMM); for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) { val = ctr_read(i); if (val < 0) { if (oprofile_running && ctr[i].enabled) { oprofile_add_ext_sample(pc, regs, i, is_kernel); ctr_write(i, reset_value[i]); } else { ctr_write(i, 0); } } } mmcr0 = mfspr(SPRN_MMCR0); /* reset the perfmon trigger */ mmcr0 |= MMCR0_PMXE; /* * We must clear the PMAO bit on some (GQ) chips. Just do it * all the time */ mmcr0 &= ~MMCR0_PMAO; /* Clear the appropriate bits in the MMCRA */ mmcra &= ~cur_cpu_spec->oprofile_mmcra_clear; mtspr(SPRN_MMCRA, mmcra); /* * now clear the freeze bit, counting will not start until we * rfid from this exception, because only at that point will * the PMM bit be cleared */ mmcr0 &= ~MMCR0_FC; mtspr(SPRN_MMCR0, mmcr0); }
bool process::update_status(trace_event ev, int signo) { pid_t pid = -1; // new pid or new LWP-id bool process_alive = true; last_event_ = ev; if (signo != _NSIG) { last_signal_ = signo; } switch (ev) { case EV_TRACING: if (is_process() && (!tracing_)) { unset_breakpoints(); unset_ret_breakpoints(); } else { uintptr_t pc = get_pc() - BREAKPOINT_INSN_LEN; adjust_call_stack_pre(pc); } pr_->function_info_printer_(*this); break; case EV_EXIT: case EV_SIG_EXIT: untrace(); process_alive = false; break; case EV_FORK: pid = tracer_.get_eventmsg(); fork_process(pid); break; case EV_CLONE: pid = tracer_.get_eventmsg(); create_thread(pid); break; case EV_SIGNALED_CRITICAL: tracer_.get_siginfo(last_signal_info_); /* fall through */ case EV_SIGNALED: pr_->signal_info_printer_(*this); break; case EV_EXEC: pr_->exec_info_printer_(*this); hoge::read_sym_set_bp(get_pid(), opts_, *this); pr_->symbol_info_printer_(*this); break; case EV_SIGSTOP: case EV_NEW: case EV_UNKNOWN: break; } return process_alive; }
void barebox_arm_reset_vector(void) { arm_cpu_lowlevel_init(); if (get_pc() > 0x80000000) goto out; arm_setup_stack(0x4030d000); pcm049_init_lowlevel(); out: barebox_arm_entry(0x80000000, SZ_512M, 0); }
void AdjustGas(Plasma &Gas,Parameter *p, int np){ int i; int nad=0, adj_type=0; for(i=0;i<np;i++){ if(strstr(p[i].s,"Gamma")){ Gas.par_Gamma=get_pc(p[i]); adj_type|=GAMMA; nad++; } else if(strstr(p[i].s,"T")){ Gas.par_T=get_pc(p[i]); adj_type|=TEMPER; nad++; } else if(strstr(p[i].s,"n")){ Gas.par_density=get_pc(p[i]); adj_type|=DENSITY; nad++; } } if(nad<2)serror("Underdefined: not enough variable plasma parameters\n"); if(nad>2)serror("Overdefined: too many contradictory variable parameters\n"); switch(adj_type){ case TEMPER|DENSITY: Gas.adjustTn(Gas.par_T,Gas.par_density); break; case TEMPER|GAMMA: Gas.adjustTG(Gas.par_T,Gas.par_Gamma); break; case GAMMA|DENSITY: Gas.adjustGn(Gas.par_Gamma,Gas.par_density); break; default: serror("Can not adjust plasma parameters.\n"); } }
void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) { omap4_save_bootinfo(data); arm_cpu_lowlevel_init(); if (get_pc() > 0x80000000) goto out; arm_setup_stack(0x4030d000); pcaaxl2_init_lowlevel(); out: barebox_arm_entry(0x80000000, SZ_512M, 0); }
void tbh(int i){ int n,m,halfwords; *((int *)(&TbH)) = i; n = TbH.rn; m = TbH.rm; if(n == 13 || Bad_Reg(m)) printf(" It is unpredictable!"); else if(InITBlock() && !LastInITBlock()) printf(" It is unpredictable!"); else{ halfwords = get_MemU(get_general_register(n) + lsl(get_general_register(m),1),1); halfwords = halfwords << 1; BranchWritePC(get_pc() + halfwords); //printf(" *****tbh"); } }
void doInfo(){ lcdClear(0xff); lcdNl(); lcdPrint("PC: "); lcdPrint(IntToStr(get_pc(),8,F_HEX));lcdNl(); lcdPrint("StackP: "); lcdPrint(IntToStr(get_sp(),8,F_HEX));lcdNl(); lcdPrint("ShadowR: "); lcdPrint(IntToStr(CREG_M4MEMMAP,8,F_HEX));lcdNl(); lcdPrint("text_s: "); lcdPrint(IntToStr((uintptr_t)&_text_start,8,F_HEX));lcdNl(); lcdPrint("bin_end: "); lcdPrint(IntToStr((uintptr_t)&_bin_end,8,F_HEX));lcdNl(); lcdPrint("bin_size:"); lcdPrint(IntToStr((uintptr_t)&_bin_size,8,F_HEX));lcdNl(); lcdPrint("reloc_ep:"); lcdPrint(IntToStr((uintptr_t)&_reloc_ep,8,F_HEX));lcdNl(); lcdPrint("end: "); lcdPrint(IntToStr((uintptr_t)&_end,8,F_HEX));lcdNl(); lcdPrint("startloc:"); lcdPrint(IntToStr(sli,8,F_HEX));lcdNl(); lcdDisplay(); getInputWait(); };
void stack_trace() { offset_t *rbp, *rip; printf("\n------ Setup Stack Trace [rsp: 0x%X | rip 0x%X]\n", get_rsp(), get_pc()); rbp = (offset_t*)get_rbp(); while(rbp && rbp < &__kernel_start__) { rip = (offset_t*)(*(rbp+1)); rbp = (offset_t*)(*rbp); printf("%X\n", (offset_t)rip); } }
static void wandboard_init(void) { unsigned long sdram_size; setup_uart(); if (get_pc() > 0x10000000) return; sdram_size = wandboard_dram_init(); pr_debug("SDRAM init finished. SDRAM size 0x%08lx\n", sdram_size); imx6_esdhc_start_image(2); pr_info("Loading image from SPI flash\n"); imx6_spi_start_image(0); }
int hal_syscall_handler(void) { CYG_ADDRWORD func, arg1, arg2, arg3, arg4; CYG_ADDRWORD err, sig; int retreg; target_register_t sr = get_register(REG_SR); if ((sr & CYGARC_SR_PM) == 0 || (sr & CYGARC_SR_BS) == 0) { // bank zero regs func = get_register(REG_B0R0); arg1 = get_register(REG_B0R1); arg2 = get_register(REG_B0R2); arg3 = get_register(REG_B0R3); arg4 = 0; retreg = REG_B0R0; } else { func = get_register(REG_B1R0); arg1 = get_register(REG_B1R1); arg2 = get_register(REG_B1R2); arg3 = get_register(REG_B1R3); retreg = REG_B1R0; } set_pc(get_pc()+2); if (func == SYS_exit) { // We want to stop in exit so that the user may poke around // to see why his app exited. return SIGTRAP; } if (func == SYS_interrupt) { // A console interrupt landed us here. // Invoke the debug agent so as to cause a SIGINT. return SIGINT; } if (__do_syscall(func, arg1, arg2, arg3, arg4, &err, &sig)) { put_register(retreg, err); return (int)sig; } return SIGTRAP; }
/** * Reads a name from the cache * * Description: * Name ::= NameStartChar (NameChar)* * NameStartChar ::= ":" | [A-Z] | "_" | [a-z] //add "?" * NameChar ::= NameStartChar | "-" | "." | [0-9] * @param var * @return RES_OK if the char was skipped, RES_EOF if no more tags, errors.. */ RES_CODE CCache::get_name(CSTRING& var) { char ch; RES_CODE res; res = get_pc(ch); if (res == RES_OK) { if (ch == ':' || ch == '_' || ch == '?' || IS_ALPHA(ch)) { var += ch; while (!var.empty()) { res = getc(ch); switch (res) { case RES_OK: if (ch == ':' || ch == '_' || ch == '-' || ch == '.' || IS_ALPHANUM(ch)) { var += ch; } else { ungetc(); return RES_OK; } break; case RES_EOF: return RES_OK; default: return (res); } } return RES_OUT_OF_MEMORY; } ungetc(); res = RES_INVALID_DATA; } return (res); }
//Address to Register adds an immediate value to the PC value, and writes the result to the destination register. void address_after_current(int i){ int imm,result,pc,base; *((int *)(&dataProAdd)) = i; imm = decode_imm12(dataProAdd.imm1,dataProAdd.imm3,dataProAdd.imm8); if(Bad_Reg(dataProAdd.rd)) printf(" it is unpredictable!"); else{ pc = get_pc(); base = align(pc,4); result = base + imm; set_general_register(dataProAdd.rd, result); #if DEBUG printf(" APSR = %X",get_apsr()); printf(" rd = %X",get_general_register(dataProAdd.rd)); printf(" ***address_after_ins\n"); #endif } }
void __bare_init __naked barebox_arm_reset_vector(void) { unsigned long r; arm_cpu_lowlevel_init(); arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 12); /* ahb lite ip interface */ writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0); writel(0xdffbfcfb, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1); writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0); writel(0xffffffff, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1); /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); if (r > 0xa0000000 && r < 0xc0000000) imx27_barebox_entry(0); /* 399 MHz */ writel(IMX_PLL_PD(0) | IMX_PLL_MFD(51) | IMX_PLL_MFI(7) | IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0); /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */ writel(IMX_PLL_PD(1) | IMX_PLL_MFD(12) | IMX_PLL_MFI(9) | IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0); writel(MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART | MX27_CSCR_ARM_SRC_MPLL | MX27_CSCR_MCU_SEL | MX27_CSCR_SP_SEL | MX27_CSCR_FPM_EN | MX27_CSCR_MPEN | MX27_CSCR_SPEN | MX27_CSCR_ARM_DIV(0) | MX27_CSCR_AHB_DIV(1) | MX27_CSCR_USB_DIV(3) | MX27_CSCR_SD_CNT(3) | MX27_CSCR_SSI2_SEL | MX27_CSCR_SSI1_SEL | MX27_CSCR_H264_SEL | MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR); sdram_init(); imx27_barebox_boot_nand_external(0); }
static noinline void imx53_guf_vincell_init(int is_lt) { void __iomem *ccm = (void *)MX53_CCM_BASE_ADDR; void __iomem *uart = IOMEM(MX53_UART2_BASE_ADDR); void *fdt; u32 r; enum bootsource src; int instance; arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8); writel(0x0088494c, ccm + MX5_CCM_CBCDR); writel(0x02b12f0a, ccm + MX5_CCM_CSCMR2); imx53_ungate_all_peripherals(); imx53_init_lowlevel_early(800); writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x27c); writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x278); imx53_uart_setup(uart); pbl_set_putc(imx_uart_putc, uart); pr_debug("GuF Vincell\n"); /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); if (!(r > 0x70000000 && r < 0xf0000000)) { disable_watchdog(); configure_dram_iomux(); imx_esdctlv4_init(); imx53_get_boot_source(&src, &instance); if (src == BOOTSOURCE_NAND && IS_ENABLED(CONFIG_MACH_GUF_VINCELL_XLOAD)) imx53_nand_start_image(); } if (is_lt) fdt = __dtb_imx53_guf_vincell_lt_start; else fdt = __dtb_imx53_guf_vincell_start; imx53_barebox_entry(fdt); }
ENTRY_FUNCTION(start_imx6_realq7, r0, r1, r2) { unsigned long sdram = 0x10000000; void *fdt; arm_cpu_lowlevel_init(); arm_setup_stack(0x00940000 - 8); fdt = __dtb_imx6q_dmo_edmqmx6_start - get_runtime_offset(); if (get_pc() < 0x10000000) { sdram_init(); mmdc_do_write_level_calibration(); mmdc_do_dqs_calibration(); } barebox_arm_entry(sdram, SZ_2G, fdt); }
void do_interrupt() { if (!in_interrupt) { in_interrupt = true; interrupt_state.pc = program_counter; interrupt_state.w = w; interrupt_state.fsr = ram( sx_ram::FSR); interrupt_state.status = ram( sx_ram::STATUS); ram( sx_ram::STATUS) &= 0x1f; // clear page bits. set_pc(0); set_nop_delay( 2); } else { if (throw_on_rtcc_overflow) { throw rtcc_overflow_exception(get_pc()); } } }
EAP_FUNC_EXPORT eap_const_string asn1_der_type_c::get_pc_string() const { #if defined(USE_EAP_DEBUG_TRACE) asn1_pc_e pc = get_pc(); if (pc == asn1_pc_primitive) { return("P"); } else if (pc == asn1_pc_constructed) { return("C"); } else #endif //#if defined(USE_EAP_DEBUG_TRACE) { return("<Unknown PC>"); } }
void ldrd(int i){ int t,t2,n,imm32,base,offset_addr,address,temp1,temp2; *((int *)(&LdrD)) = i; t = LdrD.rt; t2 = LdrD.rt2; n = LdrD.rn; imm32 = LdrD.imm8 << 2; if(LdrD.w == 1 && n == 15) printf(" It is unpredictable!"); else if(Bad_Reg(t) || Bad_Reg(t2) || t == t2) printf(" It is unpredictable!"); else{ if(n == 15) base = align(get_pc(),4); else base = get_general_register(n); if(LdrD.u == 1) offset_addr = base + imm32; else offset_addr = base - imm32; if(LdrD.p == 1) address = offset_addr; else address = get_general_register(n); if(LdrD.w == 1) set_general_register(n,offset_addr); temp1 = get_MemA(address,4); set_general_register(t,temp1); temp2 = get_MemA(address + 4,4); set_general_register(t2,temp2); #if DEBUG printf(" Rt = 0x%X",get_general_register(t)); printf(" Rt2 = 0x%X",get_general_register(t2)); printf(" *****ldrd"); #endif } }
void b_t3(int i) { /* imm32 = SignExtend(S:J2:J1:imm6:imm11:'0', 32); if cond<3:1> == '111' then SEE Branches, miscellaneous control instructions on page A4-30; if InITBlock() then UNPREDICTABLE; if ConditionPassed() then EncodingSpecificOperations(); BranchWritePC(PC + imm32); */ int imm32; *((int*)(&conditionalBranch))=i; imm32=(conditionalBranch.s<<20)|(conditionalBranch.j2<<19)|(conditionalBranch.j1<<18)| (conditionalBranch.off2<<12)|(conditionalBranch.off1<<1); imm32 &= 0xFFFFFFFE; //SignExtend if(imm32 & 0x00100000) imm32 |= 0xFFE00000; else imm32 &= 0x001FFFFF; if(conditionalBranch.cond>=14){ //question? printf("Error!Branch conditonal instruction,con<3:1>=111\n"); return; } else if(InITBlock()) printf("UNPREDICTABLE instruction\n"); else if(ConditionPassed(conditionalBranch.cond)){ EncodingSpecificOperations(); BranchWritePC(get_pc()+imm32); } }
void get_pc(int idx, int n, int r, char* str, int* p_pcnt, int* p_qcnt, int p, int q, char (*qarr)[111]) { int i; char cpystr[15]; int samecnt; if(idx == r) { //순열 (*p_pcnt)++; if(*p_pcnt == p) { // printf("-------p match :"); for(i=0; i<r; i++) { printf("%c", str[i]); } printf("\n"); return; } strcpy(cpystr, str); qsort(cpystr, r, sizeof(cpystr[0]) , compare); // 조합 // 정렬 후 중복검사 bool is_same; for(i=0; i<(*p_qcnt); i++) { samecnt = 0; is_same = false; for(int j=0; j<r; j++) { if(qarr[i][j] == cpystr[j]) { samecnt++; } } if(samecnt == r) { is_same = true; break; } } // 이미 있지 않으면 if(!is_same) { for(i=0; i<r; i++) { qarr[(*p_qcnt)][i] = str[i]; } (*p_qcnt)++; // printf("samecnt : %d, push : ", samecnt); // for(i=0; i<r; i++) { // printf("%c", str[i]); // } // printf("\n"); } if((*p_qcnt) == q) { // printf("-------q match :"); for(i=0; i<r; i++) { printf("%c", str[i]); } printf("\n"); return; } } bool is_already; for(i=0; i<n; i++) { is_already = false; // 순열 중복검사 for(int j=0; j<idx; j++) { if(str[j] == 65+i) { is_already = true; break; } } if(!is_already) { if(*p_pcnt <= p || *p_qcnt <= q) { str[idx] = 65+i; // recursive get_pc(idx+1, n, r, str, p_pcnt, p_qcnt, p, q, qarr); } } } }
asmlinkage void csyscall(struct pt_regs* regs) { unsigned long num = regs->gregs[13]; extern void stack_trace(void); extern void leave_kernel(struct pt_regs* regs); CHECK_STACK(); #if 0 if (user_mode(regs)) { printk("syscall %d; pc == 0x%8x\n", num, get_pc()); stack_trace(); } #endif if (num >= 0 && num < __NR_nocall) { switch(num) { /* * system calls that need the regs */ case __NR_fork: case __NR_clone: case __NR_execve: case __NR_sigsuspend: regs->gregs[0] = ((int (*)(int))(syscall_tab[num]))((int)regs); break; #ifdef DEBUG /* help debug user applications */ case __NR_dbg_break: printk("break: %s\n", regs->gregs[0]); system_break(); break; case __NR_dbg_hexprint: printk("value: %x\n", regs->gregs[0]); break; #endif case __NR_mmap: regs->gregs[0] = sys_mmap(regs); #if 0 dprintk("mmap: returning 0x%8x\n", regs->gregs[0]); #endif break; default: regs->gregs[0] = syscall_tab[num](regs->gregs[0], regs->gregs[1], regs->gregs[2], regs->gregs[3], regs->gregs[4]); break; } } else { regs->gregs[0] = -ENOSYS; } #if 0 printk("csyscall: returning %p\n", regs->gregs[0]); stack_trace(); #endif leave_kernel(regs); }
void __bare_init __naked barebox_arm_reset_vector(void) { uint32_t r; volatile int v; arm_cpu_lowlevel_init(); writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR); writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR); for (v = 0; v < 0x4000; v++); writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR); writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR); writel(MX31_PDR0_CSI_PODF(0xff1) | \ MX31_PDR0_PER_PODF(7) | \ MX31_PDR0_HSP_PODF(3) | \ MX31_PDR0_NFC_PODF(5) | \ MX31_PDR0_IPG_PODF(1) | \ MX31_PDR0_MAX_PODF(3) | \ MX31_PDR0_MCU_PODF(0), \ MX31_CCM_BASE_ADDR + MX31_CCM_PDR0); writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL); writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR + MX31_CCM_SPCTL); /* * Configure IOMUXC * Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched), * 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched) * (behaviour copied by sha, source unknown) */ writel(0, 0x43fac26c); writel(0, 0x43fac270); writel(0, 0x43fac274); writel(0x1000, 0x43fac27c); for (r = 0x43fac284; r <= 0x43fac2dc; r += 4) writel(0, r); /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); if (r > 0x80000000 && r < 0xa0000000) imx31_barebox_entry(0); #if defined CONFIG_PCM037_SDRAM_BANK0_128MB #define ROWS0 ESDCTL0_ROW13 #elif defined CONFIG_PCM037_SDRAM_BANK0_256MB #define ROWS0 ESDCTL0_ROW14 #endif writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0); writel(0x90100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00); writel(0xa0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writel(0x12344321, MX31_CSD0_BASE_ADDR); writel(0x12344321, MX31_CSD0_BASE_ADDR); writel(0xb0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33); writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000); writel(0x80226080 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR); writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); #ifndef CONFIG_PCM037_SDRAM_BANK1_NONE #if defined CONFIG_PCM037_SDRAM_BANK1_128MB #define ROWS1 ESDCTL0_ROW13 #elif defined CONFIG_PCM037_SDRAM_BANK1_256MB #define ROWS1 ESDCTL0_ROW14 #endif writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG1); writel(0x90100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); writel(0x12344321, MX31_CSD1_BASE_ADDR + 0xf00); writel(0xa0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); writel(0x12344321, MX31_CSD1_BASE_ADDR); writel(0x12344321, MX31_CSD1_BASE_ADDR); writel(0xb0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); writeb(0xda, MX31_CSD1_BASE_ADDR + 0x33); writeb(0xff, MX31_CSD1_BASE_ADDR + 0x01000000); writel(0x80226080 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); writel(0xDEADBEEF, MX31_CSD1_BASE_ADDR); writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); #endif #ifdef CONFIG_NAND_IMX_BOOT /* setup a stack to be able to call imx31_barebox_boot_nand_external() */ arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 12); imx31_barebox_boot_nand_external(); #else imx31_barebox_entry(0); #endif }