static int __init hd_board_init(void) { if(check_hd_param() < 0) return -EINVAL; rk_headset_info.Headset_gpio = get_port_config(hd_io).gpio; rk_headset_info.Hook_gpio = get_port_config(hk_io).gpio; return 0; }
static int __init sc_board_init(void) { if(check_sc_param() < 0) return -EINVAL; rk29_sc6610_info.bp_power = get_port_config(bp_pwr).gpio; rk29_sc6610_info.bp_reset = get_port_config(bp_rst).gpio; rk29_sc6610_info.bp_wakeup_ap = get_port_config(bp_wk_ap).gpio; rk29_sc6610_info.ap_wakeup_bp = get_port_config(ap_wk_bp).gpio; rk29_sc6610_info.modem_assert = get_port_config(mdm_asst).gpio; return 0; }
int port_get_value(unsigned int value) { struct port_config port; port = get_port_config(value); return gpio_get_value(port.gpio); }
void port_deinit(unsigned int value) { struct port_config port; port = get_port_config(value); gpio_free(port.gpio); }
void port_output_off(unsigned int value) { struct port_config port; port = get_port_config(value); gpio_set_value(port.gpio, !!port.io.active_low); }
static int __init mdm_sound_board_init(void) { struct port_config port; if(check_mdm_sound_param() < 0) return -EINVAL; port = get_port_config(spkctl_io); modem_sound_info.spkctl_io = port.gpio; modem_sound_info.spkctl_active = !port.io.active_low; return 0; }
static int ct36x_add_client(void) { int i; struct port_config ct36x_rst, ct36x_irq; ct36x_pdata.model = model; ct36x_pdata.x_max = x_max; ct36x_pdata.y_max = y_max; for(i = 0; i < 4; i++) ct36x_pdata.orientation = orientation[i]; ct36x_rst = get_port_config(rst); ct36x_pdata.rst_io.gpio = ct36x_rst.gpio; ct36x_pdata.rst_io.active_low = ct36x_rst.io.active_low; ct36x_irq = get_port_config(irq); ct36x_pdata.irq_io.gpio = ct36x_rst.gpio; ct36x_pdata.irq_io.active_low = ct36x_rst.io.active_low; ct36x_info.addr = addr; return i2c_add_device(i2c, &ct36x_info); }
int port_input_init(unsigned int value, char *name) { int ret = 0; struct port_config port; port = get_port_config(value); ret = gpio_request(port.gpio, name); if(ret < 0) return ret; if(port.io.pull_mode == PULL_MODE_DISABLE) gpio_pull_updown(port.gpio, 0); if(port.io.pull_mode == PULL_MODE_ENABLE) gpio_pull_updown(port.gpio, 1); gpio_direction_input(port.gpio); return 0; }
static int tp_hw_init(void) { int ret = 0; ret = gpio_request(get_port_config(irq).gpio, "tp_irq"); if(ret < 0){ printk("%s: gpio_request(irq gpio) failed\n", __func__); return ret; } ret = port_output_init(rst, 0, "tp_rst"); if(ret < 0){ printk("%s: port(rst) output init faild\n", __func__); return ret; } port_output_on(rst); return 0; }
static int wm831x_pre_init(struct wm831x *parm) { int ret; Wm831x = parm; printk("%s\n", __func__); #ifdef CONFIG_RK_CONFIG if(sram_gpio_init(get_port_config(pmic_slp).gpio, &pmic_sleep) < 0){ printk(KERN_ERR "sram_gpio_init failed\n"); return -EINVAL; } if(port_output_init(pmic_slp, 0, "pmic_slp") < 0){ printk(KERN_ERR "port_output_init failed\n"); return -EINVAL; } #else if(sram_gpio_init(PMU_POWER_SLEEP, &pmic_sleep) < 0){ printk(KERN_ERR "sram_gpio_init failed\n"); return -EINVAL; } gpio_request(PMU_POWER_SLEEP, "NULL"); gpio_direction_output(PMU_POWER_SLEEP, GPIO_LOW); #endif #ifdef CONFIG_WM8326_VBAT_LOW_DETECTION #ifdef CONFIG_BATTERY_RK30_VOL3V8 wm831x_set_bits(parm,WM831X_SYSVDD_CONTROL ,0xc077,0xc035); //pvdd power on dect vbat voltage printk("+++The vbat is too low+++\n"); #endif #endif ret = wm831x_reg_read(parm, WM831X_POWER_STATE) & 0xffff; wm831x_reg_write(parm, WM831X_POWER_STATE, (ret & 0xfff8) | 0x04); wm831x_set_bits(parm, WM831X_RTC_CONTROL, WM831X_RTC_ALAM_ENA_MASK, 0x0400);//enable rtc alam //BATT_FET_ENA = 1 wm831x_reg_write(parm, WM831X_SECURITY_KEY, 0x9716); // unlock security key wm831x_set_bits(parm, WM831X_RESET_CONTROL, 0x1003, 0x1001); ret = wm831x_reg_read(parm, WM831X_RESET_CONTROL) & 0xffff & UNLOCK_SECURITY_KEY; // enternal reset active in sleep // printk("%s:WM831X_RESET_CONTROL=0x%x\n", __func__, ret); wm831x_reg_write(parm, WM831X_RESET_CONTROL, ret); wm831x_set_bits(parm,WM831X_DC1_ON_CONFIG ,0x0300,0x0000); //set dcdc mode is FCCM wm831x_set_bits(parm,WM831X_DC2_ON_CONFIG ,0x0300,0x0000); wm831x_set_bits(parm,WM831X_DC3_ON_CONFIG ,0x0300,0x0000); wm831x_set_bits(parm,0x4066,0x0300,0x0000); #ifndef CONFIG_MACH_RK3066_SDK wm831x_set_bits(parm,WM831X_LDO10_CONTROL ,0x0040,0x0040);// set ldo10 in switch mode #endif wm831x_set_bits(parm,WM831X_STATUS_LED_1 ,0xc300,0xc100);// set led1 on(in manual mode) wm831x_set_bits(parm,WM831X_STATUS_LED_2 ,0xc300,0xc000);//set led2 off(in manual mode) wm831x_set_bits(parm,WM831X_LDO5_SLEEP_CONTROL ,0xe000,0x2000);// set ldo5 is disable in sleep mode wm831x_set_bits(parm,WM831X_LDO1_SLEEP_CONTROL ,0xe000,0x2000);// set ldo1 is disable in sleep mode wm831x_reg_write(parm, WM831X_SECURITY_KEY, LOCK_SECURITY_KEY); // lock security key return 0; }
static int act8846_set_init(struct act8846 *act8846) { struct regulator *dcdc; struct regulator *ldo; int i = 0; printk("%s,line=%d\n", __func__,__LINE__); #ifndef CONFIG_RK_CONFIG g_pmic_type = PMIC_TYPE_ACT8846; #endif printk("%s:g_pmic_type=%d\n",__func__,g_pmic_type); for(i = 0; i < ARRAY_SIZE(act8846_dcdc_info); i++) { if(act8846_dcdc_info[i].min_uv == 0 && act8846_dcdc_info[i].max_uv == 0) continue; dcdc =regulator_get(NULL, act8846_dcdc_info[i].name); regulator_set_voltage(dcdc, act8846_dcdc_info[i].min_uv, act8846_dcdc_info[i].max_uv); regulator_set_suspend_voltage(dcdc, act8846_dcdc_info[i].suspend_vol); regulator_enable(dcdc); printk("%s %s =%dmV end\n", __func__,act8846_dcdc_info[i].name, regulator_get_voltage(dcdc)); regulator_put(dcdc); udelay(100); } for(i = 0; i < ARRAY_SIZE(act8846_ldo_info); i++) { if(act8846_ldo_info[i].min_uv == 0 && act8846_ldo_info[i].max_uv == 0) continue; ldo =regulator_get(NULL, act8846_ldo_info[i].name); regulator_set_voltage(ldo, act8846_ldo_info[i].min_uv, act8846_ldo_info[i].max_uv); regulator_enable(ldo); printk("%s %s =%dmV end\n", __func__,act8846_ldo_info[i].name, regulator_get_voltage(ldo)); regulator_put(ldo); } #ifdef CONFIG_RK_CONFIG if(sram_gpio_init(get_port_config(pmic_slp).gpio, &pmic_sleep) < 0){ printk(KERN_ERR "sram_gpio_init failed\n"); return -EINVAL; } if(port_output_init(pmic_slp, 0, "pmic_slp") < 0){ printk(KERN_ERR "port_output_init failed\n"); return -EINVAL; } #else if(sram_gpio_init(PMU_POWER_SLEEP, &pmic_sleep) < 0){ printk(KERN_ERR "sram_gpio_init failed\n"); return -EINVAL; } gpio_request(PMU_POWER_SLEEP, "NULL"); gpio_direction_output(PMU_POWER_SLEEP, GPIO_LOW); #ifdef CONFIG_ACT8846_SUPPORT_RESET if(sram_gpio_init(PMU_VSEL, &pmic_vsel) < 0){ printk(KERN_ERR "sram_gpio_init failed\n"); return -EINVAL; } // rk30_mux_api_set(GPIO3D3_PWM0_NAME,GPIO3D_GPIO3D3); gpio_request(PMU_VSEL, "NULL"); gpio_direction_output(PMU_VSEL, GPIO_HIGH); #endif #endif printk("%s,line=%d END\n", __func__,__LINE__); return 0; }
int tps65910_pre_init(struct tps65910 *tps65910){ int val = 0; int i = 0; int err = -1; printk("%s,line=%d\n", __func__,__LINE__); #ifdef CONFIG_RK_CONFIG if(sram_gpio_init(get_port_config(pmic_slp).gpio, &pmic_sleep) < 0){ printk(KERN_ERR "sram_gpio_init failed\n"); return -EINVAL; } if(port_output_init(pmic_slp, 0, "pmic_slp") < 0){ printk(KERN_ERR "port_output_init failed\n"); return -EINVAL; } #else if(sram_gpio_init(PMU_POWER_SLEEP, &pmic_sleep) < 0){ printk(KERN_ERR "sram_gpio_init failed\n"); return -EINVAL; } gpio_request(PMU_POWER_SLEEP, "NULL"); gpio_direction_output(PMU_POWER_SLEEP, GPIO_LOW); #endif #if 0 /*************set vdd11 (pll) voltage 1.0v********************/ val = tps65910_reg_read(tps65910, TPS65910_VDIG2); if (val<0) { printk(KERN_ERR "Unable to read TPS65910_VDIG2 reg\n"); return val; } val &= (~(0x3<<2)); err = tps65910_reg_write(tps65910, TPS65910_VDIG2, val); if (err) { printk(KERN_ERR "Unable to write TPS65910_VDIG2 reg\n"); return err; } /****************************************/ #endif val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL2); if (val<0) { printk(KERN_ERR "Unable to read TPS65910_DEVCTRL2 reg\n"); return val; } /* Set sleep state active high and allow device turn-off after PWRON long press */ val |= (DEVCTRL2_SLEEPSIG_POL_MASK | DEVCTRL2_PWON_LP_OFF_MASK); err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL2, val); if (err) { printk(KERN_ERR "Unable to write TPS65910_DEVCTRL2 reg\n"); return err; } #if 1 /* set PSKIP=0 */ val = tps65910_reg_read(tps65910, TPS65910_DCDCCTRL); if (val<0) { printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n"); return val; } val &= ~DEVCTRL_DEV_OFF_MASK; val &= ~DEVCTRL_DEV_SLP_MASK; err = tps65910_reg_write(tps65910, TPS65910_DCDCCTRL, val); if (err) { printk(KERN_ERR "Unable to write TPS65910_DCDCCTRL reg\n"); return err; } #endif /* Set the maxinum load current */ /* VDD1 */ val = tps65910_reg_read(tps65910, TPS65910_VDD1); if (val<0) { printk(KERN_ERR "Unable to read TPS65910_VDD1 reg\n"); return val; } val |= (1<<5); //when 1: 1.5 A val &= (~(0x3 <<2)); val |= (0x01<<2); //TSTEP[3:2] = 01 : 12.5 mV/us(sampling 3 Mhz) err = tps65910_reg_write(tps65910, TPS65910_VDD1, val); if (err) { printk(KERN_ERR "Unable to write TPS65910_VDD1 reg\n"); return err; } /* VDD2 */ val = tps65910_reg_read(tps65910, TPS65910_VDD2); if (val<0) { printk(KERN_ERR "Unable to read TPS65910_VDD2 reg\n"); return val; } val |= (1<<5); //when 1: 1.5 A val &= (~(0x3 <<2)); val |= (0x01<<2); //TSTEP[3:2] = 01 : 12.5 mV/us(sampling 3 Mhz) err = tps65910_reg_write(tps65910, TPS65910_VDD2, val); if (err) { printk(KERN_ERR "Unable to write TPS65910_VDD2 reg\n"); return err; } /* VIO */ val = tps65910_reg_read(tps65910, TPS65910_VIO); if (val<0) { printk(KERN_ERR "Unable to read TPS65910_VIO reg\n"); return -EIO; } val |= (1<<6); //when 01: 1.0 A err = tps65910_reg_write(tps65910, TPS65910_VIO, val); if (err) { printk(KERN_ERR "Unable to write TPS65910_VIO reg\n"); return err; } #if 1 /* Mask ALL interrupts */ err = tps65910_reg_write(tps65910,TPS65910_INT_MSK, 0xFF); if (err) { printk(KERN_ERR "Unable to write TPS65910_INT_MSK reg\n"); return err; } err = tps65910_reg_write(tps65910, TPS65910_INT_MSK2, 0x03); if (err) { printk(KERN_ERR "Unable to write TPS65910_INT_MSK2 reg\n"); return err; } /* Set RTC Power, disable Smart Reflex in DEVCTRL_REG */ #if 1 val = 0; val |= (DEVCTRL_SR_CTL_I2C_SEL_MASK); err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val); if (err) { printk(KERN_ERR "Unable to write TPS65910_DEVCTRL reg\n"); return err; } printk(KERN_INFO "TPS65910 Set default voltage.\n"); #endif #if 0 //read sleep control register for debug for(i=0; i<6; i++) { err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i); if (err) { printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n"); return -EIO; } else printk("%s.......is 0x%04x\n",__FUNCTION__,val); } #endif #if 1 //sleep control register /*set func when in sleep mode */ val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL); if (val<0) { printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n"); return val; } val |= (1 << 1); err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val); if (err) { printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \ \n", TPS65910_VDIG1); return err; } /* open ldo when in sleep mode */ val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_LDO_ON); if (val<0) { printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n"); return val; } val &= 0; err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_LDO_ON, val); if (err) { printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \ \n", TPS65910_VDIG1); return err; } /*set dc mode when in sleep mode */ val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_RES_ON); if (val<0) { printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n"); return val; } val |= 0xff; val &= ~(0x07); //set vdd1 vdd2 vio in pfm mode when in sleep err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_RES_ON, val); if (err) { printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \ \n", TPS65910_VDIG1); return err; } /*close ldo when in sleep mode */ val = tps65910_reg_read(tps65910, TPS65910_SLEEP_SET_LDO_OFF); if (val<0) { printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n"); return val; } #if defined ( CONFIG_ARCH_RK3026) val |= 0x2b; #else val |= 0x0b; #endif err = tps65910_reg_write(tps65910, TPS65910_SLEEP_SET_LDO_OFF, val); if (err) { printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \ \n", TPS65910_VDIG1); return err; } #endif #if 0 //read sleep control register for debug for(i=0; i<6; i++) { err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i); if (err) { printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n"); return -EIO; } else printk("%s.......is 0x%4x\n",__FUNCTION__,val); } #endif #endif /*****************set arm and logic (dc1&dc2)in pwm ****************/ val = tps65910_reg_read(tps65910, TPS65910_DCDCCTRL); if (val<0) { printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n"); return val; } val &= ~(3<<4); err = tps65910_reg_write(tps65910, TPS65910_DCDCCTRL, val); if (err) { printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \ \n", TPS65910_VDIG1); return err; } /************************************************/ printk("%s,line=%d\n", __func__,__LINE__); return 0; }
static int rk808_set_init(struct rk808 *rk808) { struct regulator *dcdc; struct regulator *ldo; int i = 0; printk("%s,line=%d\n", __func__,__LINE__); #ifndef CONFIG_RK_CONFIG g_pmic_type = PMIC_TYPE_RK808; #endif printk("%s:g_pmic_type=%d\n",__func__,g_pmic_type); for(i = 0; i < ARRAY_SIZE(rk808_dcdc_info); i++) { if(rk808_dcdc_info[i].min_uv == 0 && rk808_dcdc_info[i].max_uv == 0) continue; dcdc =regulator_get(NULL, rk808_dcdc_info[i].name); regulator_set_voltage(dcdc, rk808_dcdc_info[i].min_uv, rk808_dcdc_info[i].max_uv); regulator_set_suspend_voltage(dcdc, rk808_dcdc_info[i].suspend_vol); regulator_enable(dcdc); printk("%s %s =%duV end\n", __func__,rk808_dcdc_info[i].name, regulator_get_voltage(dcdc)); regulator_put(dcdc); udelay(100); } for(i = 0; i < ARRAY_SIZE(rk808_ldo_info); i++) { if(rk808_ldo_info[i].min_uv == 0 && rk808_ldo_info[i].max_uv == 0) continue; ldo =regulator_get(NULL, rk808_ldo_info[i].name); regulator_set_voltage(ldo, rk808_ldo_info[i].min_uv, rk808_ldo_info[i].max_uv); regulator_set_suspend_voltage(ldo, rk808_ldo_info[i].suspend_vol); regulator_enable(ldo); printk("%s %s =%duV end\n", __func__,rk808_ldo_info[i].name, regulator_get_voltage(ldo)); regulator_put(ldo); } #ifdef CONFIG_RK_CONFIG if(sram_gpio_init(get_port_config(pmic_slp).gpio, &pmic_sleep) < 0){ printk(KERN_ERR "sram_gpio_init failed\n"); return -EINVAL; } if(port_output_init(pmic_slp, 0, "pmic_slp") < 0){ printk(KERN_ERR "port_output_init failed\n"); return -EINVAL; } #else if(sram_gpio_init(PMU_POWER_SLEEP, &pmic_sleep) < 0){ printk(KERN_ERR "sram_gpio_init failed\n"); return -EINVAL; } gpio_request(PMU_POWER_SLEEP, "NULL"); gpio_direction_output(PMU_POWER_SLEEP, GPIO_LOW); #endif printk("%s,line=%d END\n", __func__,__LINE__); return 0; }