int get_clocks (void) { volatile immap_t *immap = (immap_t *) CFG_IMMR; ulong clkin; ulong sccr, dfbrg; ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf; corecnf_t *cp; #if !defined(CONFIG_8260_CLKIN) #error clock measuring not implemented yet - define CONFIG_8260_CLKIN #else clkin = CONFIG_8260_CLKIN; #endif sccr = immap->im_clkrst.car_sccr; dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; scmr = immap->im_clkrst.car_scmr; corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT; cp = &corecnf_tab[corecnf]; busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT; cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT; /* HiP7, HiP7 Rev01, HiP7 RevA */ if ((get_pvr () == PVR_8260_HIP7) || (get_pvr () == PVR_8260_HIP7R1) || (get_pvr () == PVR_8260_HIP7RA)) { pllmf = (scmr & SCMR_PLLMF_MSKH7) >> SCMR_PLLMF_SHIFT; gd->vco_out = clkin * (pllmf + 1); } else { /* HiP3, HiP4 */
/* * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with * board specific values. */ static int ppc440spe_rev_a(void) { if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA)) return 1; else return 0; }
void video_get_info_str (int line_number, char *info) { uint pvr = get_pvr (); /* init video info strings for graphic console */ switch (line_number) { case 1: switch (pvr) { case PVR_405EP_RB: sprintf (info, " AMCC PowerPC 405EP Rev. B"); break; default: sprintf (info, " AMCC PowerPC 405EP Rev. <unknown>"); break; } return; case 2: sprintf (info, " DAVE Srl PPChameleonEVB - www.dave-tech.it"); return; case 3: sprintf (info, " %s", smi.modeIdent); return; } /* no more info lines */ *info = 0; return; }
int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { uint pvr; uint ver; unsigned long val, msr; pvr = get_pvr(); ver = PVR_VER(pvr); if (ver & 1){ /* e500 v2 core has reset control register */ volatile unsigned int * rstcr; rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0); *rstcr = 0x2; /* HRESET_REQ */ udelay(100); } /* * Fallthrough if the code above failed * Initiate hard reset in debug control register DBCR0 * Make sure MSR[DE] = 1 */ msr = mfmsr (); msr |= MSR_DE; mtmsr (msr); val = mfspr(DBCR0); val |= 0x70000000; mtspr(DBCR0,val); return 1; }
/* * initialize higher level parts of CPU like time base and timers */ int cpu_init_r (void) { #if defined(CONFIG_405GP) || defined(CONFIG_405EP) DECLARE_GLOBAL_DATA_PTR; bd_t *bd = gd->bd; unsigned long reg; #if defined(CONFIG_405GP) uint pvr = get_pvr(); #endif #ifdef CFG_INIT_DCACHE_CS /* * Flush and invalidate dcache, then disable CS for temporary stack. * Afterwards, this CS can be used for other purposes */ dcache_disable(); /* flush and invalidate dcache */ mtebc(PBxAP, 0); mtebc(PBxCR, 0); /* disable CS for temporary stack */ #if (defined(PBxAP_VAL) && defined(PBxCR_VAL)) /* * Write new value into CS register */ mtebc(PBxAP, PBxAP_VAL); mtebc(PBxCR, PBxCR_VAL); #endif #endif /* CFG_INIT_DCACHE_CS */ /* * Write Ethernetaddress into on-chip register */ reg = 0x00000000; reg |= bd->bi_enetaddr[0]; /* set high address */ reg = reg << 8; reg |= bd->bi_enetaddr[1]; out32 (EMAC_IAH, reg); reg = 0x00000000; reg |= bd->bi_enetaddr[2]; /* set low address */ reg = reg << 8; reg |= bd->bi_enetaddr[3]; reg = reg << 8; reg |= bd->bi_enetaddr[4]; reg = reg << 8; reg |= bd->bi_enetaddr[5]; out32 (EMAC_IAL, reg); #if defined(CONFIG_405GP) /* * Set edge conditioning circuitry on PPC405GPr * for compatibility to existing PPC405GP designs. */ if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) { mtdcr(ecr, 0x60606000); } #endif /* defined(CONFIG_405GP) */ #endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */ return (0); }
int ppc440spe_revB() { unsigned int pvr; pvr = get_pvr(); if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB)) return 1; else return 0; }
void local_bus_init(void) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; volatile ccsr_lbc_t *lbc = &immap->im_lbc; uint clkdiv; uint lbc_hz; sys_info_t sysinfo; /* * Errata LBC11. * Fix Local Bus clock glitch when DLL is enabled. * * If localbus freq is < 66Mhz, DLL bypass mode must be used. * If localbus freq is > 133Mhz, DLL can be safely enabled. * Between 66 and 133, the DLL is enabled with an override workaround. */ get_sys_info(&sysinfo); clkdiv = lbc->lcrr & 0x0f; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ } else if (lbc_hz >= 133) { lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ } else { /* * On REV1 boards, need to change CLKDIV before enable DLL. * Default CLKDIV is 8, change it to 4 temporarily. */ uint pvr = get_pvr(); uint temp_lbcdll = 0; if (pvr == PVR_85xx_REV1) { /* FIXME: Justify the high bit here. */ lbc->lcrr = 0x10000004; } lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */ udelay(200); /* * Sample LBC DLL ctrl reg, upshift it to set the * override bits. */ temp_lbcdll = gur->lbcdllcr; gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); asm("sync;isync;msync"); } }
/* * Check Board Identity: */ int checkboard(void) { char *s = getenv("serial#"); uint pvr = get_pvr(); if (pvr == PVR_405GPR_RB) { puts("Board: Sycamore - AMCC PPC405GPr Evaluation Board"); } else { puts("Board: Walnut - AMCC PPC405GP Evaluation Board"); } if (s != NULL) { puts(", serial# "); puts(s); } putc('\n'); return (0); }
/* * Check Board Identity: */ int checkboard(void) { char buf[64]; int i = getenv_f("serial#", buf, sizeof(buf)); uint pvr = get_pvr(); if (pvr == PVR_405GPR_RB) { puts("Board: Sycamore - AMCC PPC405GPr Evaluation Board"); } else { puts("Board: Walnut - AMCC PPC405GP Evaluation Board"); } if (i > 0) { puts(", serial# "); puts(buf); } putc('\n'); return (0); }
status_t arch_system_info_init(struct kernel_args *args) { int i; sCPUClockFrequency = args->arch_args.cpu_frequency; sBusClockFrequency = args->arch_args.bus_frequency; // The PVR (processor version register) contains processor version and // revision. sPVR = get_pvr(); uint16 model = (uint16)(sPVR >> 16); //sCPURevision = (uint16)(pvr & 0xffff); // Populate vendor for (i = 0; kCPUModels[i].vendor != B_CPU_VENDOR_UNKNOWN; i++) { if (model == kCPUModels[i].version) { sCPUVendor = kCPUModels[i].vendor; break; } } return B_OK; }
int checkcpu (void) { sys_info_t sysinfo; uint lcrr; /* local bus clock ratio register */ uint clkdiv; /* clock divider portion of lcrr */ uint pvr, svr; uint fam; uint ver; uint major, minor; struct cpu_type *cpu; #ifdef CONFIG_DDR_CLK_FREQ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; #else u32 ddr_ratio = 0; #endif svr = get_svr(); ver = SVR_SOC_VER(svr); major = SVR_MAJ(svr); #ifdef CONFIG_MPC8536 major &= 0x7; /* the msb of this nibble is a mfg code */ #endif minor = SVR_MIN(svr); puts("CPU: "); cpu = identify_cpu(ver); if (cpu) { puts(cpu->name); if (IS_E_PROCESSOR(svr)) puts("E"); } else { puts("Unknown"); } printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); fam = PVR_FAM(pvr); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); printf("Core: "); switch (fam) { case PVR_FAM(PVR_85xx): puts("E500"); break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); get_sys_info(&sysinfo); puts("Clock Configuration:\n"); printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000)); printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000)); switch (ddr_ratio) { case 0x0: printf(" DDR:%4lu MHz (%lu MT/s data rate), ", DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000)); break; case 0x7: printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ", DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000)); break; default: printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ", DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000)); break; } #if defined(CFG_LBC_LCRR) lcrr = CFG_LBC_LCRR; #else { volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); lcrr = lbc->lcrr; } #endif clkdiv = lcrr & 0x0f; if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { #if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \ defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536) /* * Yes, the entire PQ38 family use the same * bit-representation for twice the clock divider values. */ clkdiv *= 2; #endif printf("LBC:%4lu MHz\n", DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv); } else { printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr); } #ifdef CONFIG_CPM2 printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000); #endif puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); return 0; }
int checkcpu(void) { sys_info_t sysinfo; uint pvr, svr; uint major, minor; char buf1[32], buf2[32]; volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; struct cpu_type *cpu; uint msscr0 = mfspr(MSSCR0); svr = get_svr(); major = SVR_MAJ(svr); minor = SVR_MIN(svr); if (cpu_numcores() > 1) { #ifndef CONFIG_MP puts("Unicore software on multiprocessor system!!\n" "To enable mutlticore build define CONFIG_MP\n"); #endif } puts("CPU: "); cpu = gd->arch.cpu; puts(cpu->name); printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); puts("Core: "); pvr = get_pvr(); major = PVR_E600_MAJ(pvr); minor = PVR_E600_MIN(pvr); printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0); if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE) puts("\n Core1Translation Enabled"); debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr); printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); get_sys_info(&sysinfo); puts("Clock Configuration:\n"); printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor)); printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); printf(" DDR:%-4s MHz (%s MT/s data rate), ", strmhz(buf1, sysinfo.freqSystemBus / 2), strmhz(buf2, sysinfo.freqSystemBus)); if (sysinfo.freqLocalBus > LCRR_CLKDIV) { printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freqLocalBus); } puts("L1: D-cache 32 KB enabled\n"); puts(" I-cache 32 KB enabled\n"); puts("L2: "); if (get_l2cr() & 0x80000000) { #if defined(CONFIG_MPC8610) puts("256"); #elif defined(CONFIG_MPC8641) puts("512"); #endif puts(" KB enabled\n"); } else { puts("Disabled\n"); } return 0; }
int checkcpu (void) { sys_info_t sysinfo; uint pvr, svr; uint fam; uint ver; uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif /* CONFIG_FSL_CORENET */ #ifdef CONFIG_DDR_CLK_FREQ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else #ifdef CONFIG_FSL_CORENET u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; #else u32 ddr_ratio = 0; #endif /* CONFIG_FSL_CORENET */ #endif /* CONFIG_DDR_CLK_FREQ */ int i; svr = get_svr(); major = SVR_MAJ(svr); #ifdef CONFIG_MPC8536 major &= 0x7; /* the msb of this nibble is a mfg code */ #endif minor = SVR_MIN(svr); if (cpu_numcores() > 1) { #ifndef CONFIG_MP puts("Unicore software on multiprocessor system!!\n" "To enable mutlticore build define CONFIG_MP\n"); #endif volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); printf("CPU%d: ", pic->whoami); } else { puts("CPU: "); } cpu = gd->cpu; puts(cpu->name); if (IS_E_PROCESSOR(svr)) puts("E"); printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); fam = PVR_FAM(pvr); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); printf("Core: "); if (PVR_FAM(PVR_85xx)) { switch(PVR_MEM(pvr)) { case 0x1: case 0x2: puts("E500"); break; case 0x3: puts("E500MC"); break; case 0x4: puts("E5500"); break; default: puts("Unknown"); break; } } else { puts("Unknown"); } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); get_sys_info(&sysinfo); puts("Clock Configuration:"); for (i = 0; i < cpu_numcores(); i++) { if (!(i & 3)) printf ("\n "); printf("CPU%d:%-4s MHz, ", i,strmhz(buf1, sysinfo.freqProcessor[i])); } printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); #ifdef CONFIG_FSL_CORENET if (ddr_sync == 1) { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); } else { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); } #else switch (ddr_ratio) { case 0x0: printf(" DDR:%-4s MHz (%s MT/s data rate), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; case 0x7: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; default: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; } #endif #if defined(CONFIG_FSL_LBC) if (sysinfo.freqLocalBus > LCRR_CLKDIV) { printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freqLocalBus); } #endif #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); #endif #ifdef CONFIG_QE printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); #endif #ifdef CONFIG_SYS_DPAA_FMAN for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { printf(" FMAN%d: %s MHz\n", i + 1, strmhz(buf1, sysinfo.freqFMan[i])); } #endif #ifdef CONFIG_SYS_DPAA_PME printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); #endif puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); return 0; }
int checkcpu (void) { sys_info_t sysinfo; uint pvr, svr; uint ver; uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif /* * Cornet platforms use ddr sync bit in RCW to indicate sync vs async * mode. Previous platform use ddr ratio to do the same. This * information is only for display here. */ #ifdef CONFIG_FSL_CORENET #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 u32 ddr_sync = 0; /* only async mode is supported */ #else u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #else /* CONFIG_FSL_CORENET */ #ifdef CONFIG_DDR_CLK_FREQ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else u32 ddr_ratio = 0; #endif /* CONFIG_DDR_CLK_FREQ */ #endif /* CONFIG_FSL_CORENET */ unsigned int i, core, nr_cores = cpu_numcores(); u32 mask = cpu_mask(); svr = get_svr(); major = SVR_MAJ(svr); minor = SVR_MIN(svr); if (cpu_numcores() > 1) { #ifndef CONFIG_MP puts("Unicore software on multiprocessor system!!\n" "To enable mutlticore build define CONFIG_MP\n"); #endif volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); printf("CPU%d: ", pic->whoami); } else { puts("CPU: "); } cpu = gd->arch.cpu; puts(cpu->name); if (IS_E_PROCESSOR(svr)) puts("E"); printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); printf("Core: "); switch(ver) { case PVR_VER_E500_V1: case PVR_VER_E500_V2: puts("e500"); break; case PVR_VER_E500MC: puts("e500mc"); break; case PVR_VER_E5500: puts("e5500"); break; case PVR_VER_E6500: puts("e6500"); break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); if (nr_cores > CONFIG_MAX_CPUS) { panic("\nUnexpected number of cores: %d, max is %d\n", nr_cores, CONFIG_MAX_CPUS); } get_sys_info(&sysinfo); puts("Clock Configuration:"); for_each_cpu(i, core, nr_cores, mask) { if (!(i & 3)) printf ("\n "); printf("CPU%d:%-4s MHz, ", core, strmhz(buf1, sysinfo.freqProcessor[core])); } printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); #ifdef CONFIG_FSL_CORENET if (ddr_sync == 1) { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); } else { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); } #else switch (ddr_ratio) { case 0x0: printf(" DDR:%-4s MHz (%s MT/s data rate), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; case 0x7: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; default: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; } #endif #if defined(CONFIG_FSL_LBC) if (sysinfo.freqLocalBus > LCRR_CLKDIV) { printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freqLocalBus); } #endif #if defined(CONFIG_FSL_IFC) printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); #endif #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); #endif #ifdef CONFIG_QE printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); #endif #ifdef CONFIG_SYS_DPAA_FMAN for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { printf(" FMAN%d: %s MHz\n", i + 1, strmhz(buf1, sysinfo.freqFMan[i])); } #endif #ifdef CONFIG_SYS_DPAA_QBMAN printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freqQMAN)); #endif #ifdef CONFIG_SYS_DPAA_PME printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); #endif puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); #ifdef CONFIG_FSL_CORENET /* Display the RCW, so that no one gets confused as to what RCW * we're actually using for this boot. */ puts("Reset Configuration Word (RCW):"); for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { u32 rcw = in_be32(&gur->rcwsr[i]); if ((i % 4) == 0) printf("\n %08x:", i * 4); printf(" %08x", rcw); } puts("\n"); #endif return 0; }
/* * Initialize Local Bus */ void local_bus_init (void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint lbc_mhz = get_lbc_clock () / 1000000; #ifdef CONFIG_MPC8548 uint svr = get_svr (); uint lcrr; /* * MPC revision < 2.0 * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1: * Modify engineering use only register at address 0xE_0F20. * "1. Read register at offset 0xE_0F20 * 2. And value with 0x0000_FFFF * 3. OR result with 0x0000_0004 * 4. Write result back to offset 0xE_0F20." * * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2: * Modify engineering use only register at address 0xE_0F20. * "1. Read register at offset 0xE_0F20 * 2. And value with 0xFFFF_FFDF * 3. Write result back to offset 0xE_0F20." * * Since it is the same register, we do the modification in one step. */ if (SVR_MAJ (svr) < 2) { uint dummy = gur->lbiuiplldcr1; dummy &= 0x0000FFDF; dummy |= 0x00000004; gur->lbiuiplldcr1 = dummy; } lcrr = CONFIG_SYS_LBC_LCRR; /* * Local Bus Clock > 83.3 MHz. According to timing * specifications set LCRR[EADC] to 2 delay cycles. */ if (lbc_mhz > 83) { lcrr &= ~LCRR_EADC; lcrr |= LCRR_EADC_2; } /* * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30 * disable PLL bypass for Local Bus Clock > 83 MHz. */ if (lbc_mhz >= 66) lcrr &= (~LCRR_DBYP); /* DLL Enabled */ else lcrr |= LCRR_DBYP; /* DLL Bypass */ lbc->lcrr = lcrr; asm ("sync;isync;msync"); /* * According to MPC8548ERMAD Rev.1.3 read back LCRR * and terminate with isync */ lcrr = lbc->lcrr; asm ("isync;"); /* let DLL stabilize */ udelay (500); #else /* !CONFIG_MPC8548 */ /* * Errata LBC11. * Fix Local Bus clock glitch when DLL is enabled. * * If localbus freq is < 66MHz, DLL bypass mode must be used. * If localbus freq is > 133MHz, DLL can be safely enabled. * Between 66 and 133, the DLL is enabled with an override workaround. */ if (lbc_mhz < 66) { lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA | LTEDR_RAWA | LTEDR_CSD; /* Disable all error checking */ } else if (lbc_mhz >= 133) { lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ } else { /* * On REV1 boards, need to change CLKDIV before enable DLL. * Default CLKDIV is 8, change it to 4 temporarily. */ uint pvr = get_pvr (); uint temp_lbcdll = 0; if (pvr == PVR_85xx_REV1) { /* FIXME: Justify the high bit here. */ lbc->lcrr = 0x10000004; } lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ udelay (200); /* * Sample LBC DLL ctrl reg, upshift it to set the * override bits. */ temp_lbcdll = gur->lbcdllcr; gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); asm ("sync;isync;msync"); } #endif /* !CONFIG_MPC8548 */ #ifdef CONFIG_CAN_DRIVER /* * According to timing specifications EAD must be * set if Local Bus Clock is > 83 MHz. */ if (lbc_mhz > 83) set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD); else set_lbc_or(2, CONFIG_SYS_OR2_CAN); set_lbc_br(2, CONFIG_SYS_BR2_CAN); /* LGPL4 is UPWAIT */ out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X); /* Initialize UPMC for CAN: single read */ upmc_write (0x00, 0xFFFFED00); upmc_write (0x01, 0xCCFFCC00); upmc_write (0x02, 0x00FFCF00); upmc_write (0x03, 0x00FFCF00); upmc_write (0x04, 0x00FFDC00); upmc_write (0x05, 0x00FFCF00); upmc_write (0x06, 0x00FFED00); upmc_write (0x07, 0x3FFFCC07); /* Initialize UPMC for CAN: single write */ upmc_write (0x18, 0xFFFFED00); upmc_write (0x19, 0xCCFFEC00); upmc_write (0x1A, 0x00FFED80); upmc_write (0x1B, 0x00FFED80); upmc_write (0x1C, 0x00FFFC00); upmc_write (0x1D, 0x0FFFEC00); upmc_write (0x1E, 0x0FFFEF00); upmc_write (0x1F, 0x3FFFEC05); #endif /* CONFIG_CAN_DRIVER */ }
int checkcpu(void) { sys_info_t sysinfo; uint pvr, svr; uint ver; uint major, minor; uint lcrr; /* local bus clock ratio register */ uint clkdiv; /* clock divider portion of lcrr */ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; puts("Freescale PowerPC\n"); pvr = get_pvr(); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); puts("CPU:\n"); puts(" Core: "); switch (ver) { case PVR_VER(PVR_86xx): { uint msscr0 = mfspr(MSSCR0); printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 ); if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE) puts("\n Core1Translation Enabled"); debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr); } break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); svr = get_svr(); ver = SVR_SOC_VER(svr); major = SVR_MAJ(svr); minor = SVR_MIN(svr); puts(" System: "); switch (ver) { case SVR_8641: if (SVR_SUBVER(svr) == 1) { puts("8641D"); } else { puts("8641"); } break; case SVR_8610: puts("8610"); break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); get_sys_info(&sysinfo); puts(" Clocks: "); printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000); printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); #if defined(CONFIG_SYS_LBC_LCRR) lcrr = CONFIG_SYS_LBC_LCRR; #else { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ccsr_lbc_t *lbc = &immap->im_lbc; lcrr = lbc->lcrr; } #endif clkdiv = lcrr & 0x0f; if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { printf("LBC:%4lu MHz\n", sysinfo.freqSystemBus / 1000000 / clkdiv); } else { printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr); } puts(" L2: "); if (get_l2cr() & 0x80000000) puts("Enabled\n"); else puts("Disabled\n"); return 0; }
int checkcpu (void) { sys_info_t sysinfo; uint pvr, svr; uint fam; uint ver; uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; #ifdef CONFIG_DDR_CLK_FREQ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else u32 ddr_ratio = 0; #endif int i; svr = get_svr(); ver = SVR_SOC_VER(svr); major = SVR_MAJ(svr); #ifdef CONFIG_MPC8536 major &= 0x7; /* the msb of this nibble is a mfg code */ #endif minor = SVR_MIN(svr); #if (CONFIG_NUM_CPUS > 1) volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); printf("CPU%d: ", pic->whoami); #else puts("CPU: "); #endif cpu = identify_cpu(ver); if (cpu) { puts(cpu->name); if (IS_E_PROCESSOR(svr)) puts("E"); } else { puts("Unknown"); } printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); fam = PVR_FAM(pvr); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); printf("Core: "); switch (fam) { case PVR_FAM(PVR_85xx): puts("E500"); break; default: puts("Unknown"); break; } if (PVR_MEM(pvr) == 0x03) puts("MC"); printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); get_sys_info(&sysinfo); puts("Clock Configuration:"); for (i = 0; i < CONFIG_NUM_CPUS; i++) { if (!(i & 3)) printf ("\n "); printf("CPU%d:%-4s MHz, ", i,strmhz(buf1, sysinfo.freqProcessor[i])); } printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); switch (ddr_ratio) { case 0x0: printf(" DDR:%-4s MHz (%s MT/s data rate), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; case 0x7: printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; default: printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; } if (sysinfo.freqLocalBus > LCRR_CLKDIV) printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); else printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freqLocalBus); #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); #endif #ifdef CONFIG_QE printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); #endif puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); return 0; }
unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) { unsigned int tlb_size; unsigned int ram_tlb_index; unsigned int ram_tlb_address; /* * Determine size of each TLB1 entry. */ switch (memsize_in_meg) { case 16: case 32: tlb_size = BOOKE_PAGESZ_16M; break; case 64: case 128: tlb_size = BOOKE_PAGESZ_64M; break; case 256: case 512: tlb_size = BOOKE_PAGESZ_256M; break; case 1024: case 2048: if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx)) tlb_size = BOOKE_PAGESZ_1G; else tlb_size = BOOKE_PAGESZ_256M; break; default: puts("DDR: only 16M, 32M, 64M, 128M, 256M, 512M, 1G" " and 2G are supported.\n"); /* * The memory was not able to be mapped. * Default to a small size. */ tlb_size = BOOKE_PAGESZ_64M; memsize_in_meg = 64; break; } /* * Configure DDR TLB1 entries. * Starting at TLB1 8, use no more than 8 TLB1 entries. */ ram_tlb_index = 8; ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; while (ram_tlb_address < (memsize_in_meg * 1024 * 1024) && ram_tlb_index < 16) { set_tlb(1, ram_tlb_address, ram_tlb_address, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, ram_tlb_index, tlb_size, 1); ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2)); ram_tlb_index++; } /* * Confirm that the requested amount of memory was mapped. */ return memsize_in_meg; }
int checkcpu (void) { #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */ uint pvr = get_pvr(); ulong clock = gd->cpu_clk; char buf[32]; #if !defined(CONFIG_IOP480) char addstr[64] = ""; sys_info_t sys_info; puts ("CPU: "); get_sys_info(&sys_info); puts("AMCC PowerPC 4"); #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ defined(CONFIG_405EX) puts("05"); #endif #if defined(CONFIG_440) puts("40"); #endif switch (pvr) { case PVR_405GP_RB: puts("GP Rev. B"); break; case PVR_405GP_RC: puts("GP Rev. C"); break; case PVR_405GP_RD: puts("GP Rev. D"); break; #ifdef CONFIG_405GP case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */ puts("GP Rev. E"); break; #endif case PVR_405CR_RA: puts("CR Rev. A"); break; case PVR_405CR_RB: puts("CR Rev. B"); break; #ifdef CONFIG_405CR case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */ puts("CR Rev. C"); break; #endif case PVR_405GPR_RB: puts("GPr Rev. B"); break; case PVR_405EP_RB: puts("EP Rev. B"); break; case PVR_405EZ_RA: puts("EZ Rev. A"); break; case PVR_405EX1_RA: puts("EX Rev. A"); strcpy(addstr, "Security support"); break; case PVR_405EX2_RA: puts("EX Rev. A"); strcpy(addstr, "No Security support"); break; case PVR_405EXR1_RA: puts("EXr Rev. A"); strcpy(addstr, "Security support"); break; case PVR_405EXR2_RA: puts("EXr Rev. A"); strcpy(addstr, "No Security support"); break; #if defined(CONFIG_440) case PVR_440GP_RB: puts("GP Rev. B"); /* See errata 1.12: CHIP_4 */ if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) || (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){ puts ( "\n\t CPC0_SYSx DCRs corrupted. " "Resetting chip ...\n"); udelay( 1000 * 1000 ); /* Give time for serial buf to clear */ do_chip_reset ( mfdcr(cpc0_strp0), mfdcr(cpc0_strp1) ); } break; case PVR_440GP_RC: puts("GP Rev. C"); break; case PVR_440GX_RA: puts("GX Rev. A"); break; case PVR_440GX_RB: puts("GX Rev. B"); break; case PVR_440GX_RC: puts("GX Rev. C"); break; case PVR_440GX_RF: puts("GX Rev. F"); break; case PVR_440EP_RA: puts("EP Rev. A"); break; #ifdef CONFIG_440EP case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */ puts("EP Rev. B"); break; case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */ puts("EP Rev. C"); break; #endif /* CONFIG_440EP */ #ifdef CONFIG_440GR case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */ puts("GR Rev. A"); break; case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */ puts("GR Rev. B"); break; #endif /* CONFIG_440GR */ #endif /* CONFIG_440 */ #ifdef CONFIG_440EPX case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ puts("EPx Rev. A"); strcpy(addstr, "Security/Kasumi support"); break; case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ puts("EPx Rev. A"); strcpy(addstr, "No Security/Kasumi support"); break; #endif /* CONFIG_440EPX */ #ifdef CONFIG_440GRX case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ puts("GRx Rev. A"); strcpy(addstr, "Security/Kasumi support"); break; case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ puts("GRx Rev. A"); strcpy(addstr, "No Security/Kasumi support"); break; #endif /* CONFIG_440GRX */ case PVR_440SP_6_RAB: puts("SP Rev. A/B"); strcpy(addstr, "RAID 6 support"); break; case PVR_440SP_RAB: puts("SP Rev. A/B"); strcpy(addstr, "No RAID 6 support"); break; case PVR_440SP_6_RC: puts("SP Rev. C"); strcpy(addstr, "RAID 6 support"); break; case PVR_440SP_RC: puts("SP Rev. C"); strcpy(addstr, "No RAID 6 support"); break; case PVR_440SPe_6_RA: puts("SPe Rev. A"); strcpy(addstr, "RAID 6 support"); break; case PVR_440SPe_RA: puts("SPe Rev. A"); strcpy(addstr, "No RAID 6 support"); break; case PVR_440SPe_6_RB: puts("SPe Rev. B"); strcpy(addstr, "RAID 6 support"); break; case PVR_440SPe_RB: puts("SPe Rev. B"); strcpy(addstr, "No RAID 6 support"); break; default: printf (" UNKNOWN (PVR=%08x)", pvr); break; } printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock), sys_info.freqPLB / 1000000, get_OPB_freq() / 1000000, sys_info.freqEBC / 1000000); if (addstr[0] != 0) printf(" %s\n", addstr); #if defined(I2C_BOOTROM) printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis"); #endif /* I2C_BOOTROM */ #if defined(SDR0_PINSTP_SHIFT) printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]); printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]); #endif /* SDR0_PINSTP_SHIFT */ #if defined(CONFIG_PCI) && !defined(CONFIG_405EX) printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis"); #endif #if defined(PCI_ASYNC) if (pci_async_enabled()) { printf (", PCI async ext clock used"); } else { printf (", PCI sync clock at %lu MHz", sys_info.freqPLB / sys_info.pllPciDiv / 1000000); } #endif #if defined(CONFIG_PCI) && !defined(CONFIG_405EX) putc('\n'); #endif #if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) printf (" 16 kB I-Cache 16 kB D-Cache"); #elif defined(CONFIG_440) printf (" 32 kB I-Cache 32 kB D-Cache"); #else printf (" 16 kB I-Cache %d kB D-Cache", ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8); #endif #endif /* !defined(CONFIG_IOP480) */ #if defined(CONFIG_IOP480) printf ("PLX IOP480 (PVR=%08x)", pvr); printf (" at %s MHz:", strmhz(buf, clock)); printf (" %u kB I-Cache", 4); printf (" %u kB D-Cache", 2); #endif #endif /* !defined(CONFIG_405) */ putc ('\n'); return 0; }
void get_sys_info (PPC405_SYS_INFO * sysInfo) { unsigned long pllmr; unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000); uint pvr = get_pvr(); unsigned long psr; unsigned long m; /* * Read PLL Mode register */ pllmr = mfdcr (pllmd); /* * Read Pin Strapping register */ psr = mfdcr (strap); /* * Determine FWD_DIV. */ sysInfo->pllFwdDiv = 8 - ((pllmr & PLLMR_FWD_DIV_MASK) >> 29); /* * Determine FBK_DIV. */ sysInfo->pllFbkDiv = ((pllmr & PLLMR_FB_DIV_MASK) >> 25); if (sysInfo->pllFbkDiv == 0) { sysInfo->pllFbkDiv = 16; } /* * Determine PLB_DIV. */ sysInfo->pllPlbDiv = ((pllmr & PLLMR_CPU_TO_PLB_MASK) >> 17) + 1; /* * Determine PCI_DIV. */ sysInfo->pllPciDiv = ((pllmr & PLLMR_PCI_TO_PLB_MASK) >> 13) + 1; /* * Determine EXTBUS_DIV. */ sysInfo->pllExtBusDiv = ((pllmr & PLLMR_EXB_TO_PLB_MASK) >> 11) + 2; /* * Determine OPB_DIV. */ sysInfo->pllOpbDiv = ((pllmr & PLLMR_OPB_TO_PLB_MASK) >> 15) + 1; /* * Check if PPC405GPr used (mask minor revision field) */ if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) { /* * Determine FWD_DIV B (only PPC405GPr with new mode strapping). */ sysInfo->pllFwdDivB = 8 - (pllmr & PLLMR_FWDB_DIV_MASK); /* * Determine factor m depending on PLL feedback clock source */ if (!(psr & PSR_PCI_ASYNC_EN)) { if (psr & PSR_NEW_MODE_EN) { /* * sync pci clock used as feedback (new mode) */ m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllPciDiv; } else { /* * sync pci clock used as feedback (legacy mode) */ m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllPciDiv; } } else if (psr & PSR_NEW_MODE_EN) { if (psr & PSR_PERCLK_SYNC_MODE_EN) { /* * PerClk used as feedback (new mode) */ m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllExtBusDiv; } else { /* * CPU clock used as feedback (new mode) */ m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv; } } else if (sysInfo->pllExtBusDiv == sysInfo->pllFbkDiv) { /* * PerClk used as feedback (legacy mode) */ m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllExtBusDiv; } else { /* * PLB clock used as feedback (legacy mode) */ m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv; } sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) / (unsigned long long)sysClkPeriodPs; sysInfo->freqProcessor = sysInfo->freqVCOHz / sysInfo->pllFwdDiv; sysInfo->freqPLB = sysInfo->freqVCOHz / (sysInfo->pllFwdDivB * sysInfo->pllPlbDiv); } else { /* * Check pllFwdDiv to see if running in bypass mode where the CPU speed * is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO * to make sure it is within the proper range. * spec: VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV * Note freqVCO is calculated in Mhz to avoid errors introduced by rounding. */ if (sysInfo->pllFwdDiv == 1) { sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ; sysInfo->freqPLB = CONFIG_SYS_CLK_FREQ / sysInfo->pllPlbDiv; } else { sysInfo->freqVCOHz = ( 1000000000000LL * (unsigned long long)sysInfo->pllFwdDiv * (unsigned long long)sysInfo->pllFbkDiv * (unsigned long long)sysInfo->pllPlbDiv ) / (unsigned long long)sysClkPeriodPs; sysInfo->freqPLB = (ONE_BILLION / ((sysClkPeriodPs * 10) / sysInfo->pllFbkDiv)) * 10000; sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv; } } }
void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu) { struct pvr_s pvr; int temp; /* for saving temp value */ get_pvr(&pvr); CI(ver_code, VERSION); if (!ci->ver_code) { pr_err("ERROR: MB has broken PVR regs -> use DTS setting\n"); return; } temp = PVR_USE_BARREL(pvr) | PVR_USE_MSR_INSTR(pvr) | PVR_USE_PCMP_INSTR(pvr) | PVR_USE_DIV(pvr); if (ci->use_instr != temp) err_printk("BARREL, MSR, PCMP or DIV"); ci->use_instr = temp; temp = PVR_USE_HW_MUL(pvr) | PVR_USE_MUL64(pvr); if (ci->use_mult != temp) err_printk("HW_MUL"); ci->use_mult = temp; temp = PVR_USE_FPU(pvr) | PVR_USE_FPU2(pvr); if (ci->use_fpu != temp) err_printk("HW_FPU"); ci->use_fpu = temp; ci->use_exc = PVR_OPCODE_0x0_ILLEGAL(pvr) | PVR_UNALIGNED_EXCEPTION(pvr) | PVR_ILL_OPCODE_EXCEPTION(pvr) | PVR_IOPB_BUS_EXCEPTION(pvr) | PVR_DOPB_BUS_EXCEPTION(pvr) | PVR_DIV_ZERO_EXCEPTION(pvr) | PVR_FPU_EXCEPTION(pvr) | PVR_FSL_EXCEPTION(pvr); CI(pvr_user1, USER1); CI(pvr_user2, USER2); CI(mmu, USE_MMU); CI(mmu_privins, MMU_PRIVINS); CI(endian, ENDIAN); CI(use_icache, USE_ICACHE); CI(icache_tagbits, ICACHE_ADDR_TAG_BITS); CI(icache_write, ICACHE_ALLOW_WR); ci->icache_line_length = PVR_ICACHE_LINE_LEN(pvr) << 2; CI(icache_size, ICACHE_BYTE_SIZE); CI(icache_base, ICACHE_BASEADDR); CI(icache_high, ICACHE_HIGHADDR); CI(use_dcache, USE_DCACHE); CI(dcache_tagbits, DCACHE_ADDR_TAG_BITS); CI(dcache_write, DCACHE_ALLOW_WR); ci->dcache_line_length = PVR_DCACHE_LINE_LEN(pvr) << 2; CI(dcache_size, DCACHE_BYTE_SIZE); CI(dcache_base, DCACHE_BASEADDR); CI(dcache_high, DCACHE_HIGHADDR); temp = PVR_DCACHE_USE_WRITEBACK(pvr); if (ci->dcache_wb != temp) err_printk("DCACHE WB"); ci->dcache_wb = temp; CI(use_dopb, D_OPB); CI(use_iopb, I_OPB); CI(use_dlmb, D_LMB); CI(use_ilmb, I_LMB); CI(num_fsl, FSL_LINKS); CI(irq_edge, INTERRUPT_IS_EDGE); CI(irq_positive, EDGE_IS_POSITIVE); CI(area_optimised, AREA_OPTIMISED); CI(hw_debug, DEBUG_ENABLED); CI(num_pc_brk, NUMBER_OF_PC_BRK); CI(num_rd_brk, NUMBER_OF_RD_ADDR_BRK); CI(num_wr_brk, NUMBER_OF_WR_ADDR_BRK); CI(fpga_family_code, TARGET_FAMILY); }
int checkcpu(void) { sys_info_t sysinfo; uint pvr, svr; uint ver; uint major, minor; uint lcrr; /* local bus clock ratio register */ uint clkdiv; /* clock divider portion of lcrr */ puts("Freescale PowerPC\n"); pvr = get_pvr(); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); puts("CPU:\n"); puts(" Core: "); switch (ver) { case PVR_VER(PVR_86xx): puts("E600"); break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); svr = get_svr(); ver = SVR_VER(svr); major = SVR_MAJ(svr); minor = SVR_MIN(svr); puts(" System: "); switch (ver) { case SVR_8641: if (SVR_SUBVER(svr) == 1) { puts("8641D"); } else { puts("8641"); } break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); get_sys_info(&sysinfo); puts(" Clocks: "); printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000); printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); #if defined(CFG_LBC_LCRR) lcrr = CFG_LBC_LCRR; #else { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile ccsr_lbc_t *lbc = &immap->im_lbc; lcrr = lbc->lcrr; } #endif clkdiv = lcrr & 0x0f; if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { printf("LBC:%4lu MHz\n", sysinfo.freqSystemBus / 1000000 / clkdiv); } else { printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr); } puts(" L2: "); if (get_l2cr() & 0x80000000) puts("Enabled\n"); else puts("Disabled\n"); return 0; }
void fpga_init(void) { unsigned long group; unsigned long sdr0_pfc0; unsigned long sdr0_pfc1; unsigned long sdr0_cust0; unsigned long pvr; mfsdr (SDR0_PFC0, sdr0_pfc0); mfsdr (SDR0_PFC1, sdr0_pfc1); group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1); pvr = get_pvr (); sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE; if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) { sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE; sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | FPGA_REG2_EXT_INTFACE_ENABLE); mtsdr (SDR0_PFC0, sdr0_pfc0); mtsdr (SDR0_PFC1, sdr0_pfc1); } else { sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE; switch (group) { case 0: case 1: case 2: /* CPU trace A */ out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | FPGA_REG2_EXT_INTFACE_ENABLE); sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; mtsdr (SDR0_PFC0, sdr0_pfc0); mtsdr (SDR0_PFC1, sdr0_pfc1); break; case 3: case 4: case 5: case 6: /* CPU trace B - Over EBMI */ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE; mtsdr (SDR0_PFC0, sdr0_pfc0); mtsdr (SDR0_PFC1, sdr0_pfc1); out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | FPGA_REG2_EXT_INTFACE_DISABLE); break; } } /* Initialize the ethernet specific functions in the fpga */ mfsdr(SDR0_PFC1, sdr0_pfc1); mfsdr(SDR0_CUST0, sdr0_cust0); if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) && ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) || (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI))) { if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) { out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) | FPGA_REG3_ENET_GROUP7); } else { if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) { out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | FPGA_REG3_ENET_GROUP7); } else { out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | FPGA_REG3_ENET_GROUP8); } } } else { if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) { out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) | FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1))); } else { out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1))); } } out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 | FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 | FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS); /* reset the gigabyte phy if necessary */ if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3) { if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) { out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE); udelay(10000); out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE); } else { out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE); udelay(10000); out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE); } } /* * new Ocotea with Rev. F (pass 3) chips has SMII PHY reset */ if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) { out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE); udelay(10000); out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE); } /* Turn off the LED's */ out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) | FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB | FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB); return; }
int checkcpu (void) { sys_info_t sysinfo; uint pvr, svr; uint ver; uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif /* * Cornet platforms use ddr sync bit in RCW to indicate sync vs async * mode. Previous platform use ddr ratio to do the same. This * information is only for display here. */ #ifdef CONFIG_FSL_CORENET #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 u32 ddr_sync = 0; /* only async mode is supported */ #else u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #else /* CONFIG_FSL_CORENET */ #ifdef CONFIG_DDR_CLK_FREQ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else u32 ddr_ratio = 0; #endif /* CONFIG_DDR_CLK_FREQ */ #endif /* CONFIG_FSL_CORENET */ unsigned int i, core, nr_cores = cpu_numcores(); u32 mask = cpu_mask(); #ifdef CONFIG_HETROGENOUS_CLUSTERS unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores(); u32 dsp_mask = cpu_dsp_mask(); #endif svr = get_svr(); major = SVR_MAJ(svr); minor = SVR_MIN(svr); #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) if (SVR_SOC_VER(svr) == SVR_T4080) { ccsr_rcpm_t *rcpm = (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 || FSL_CORENET_DEVDISR2_DTSEC1_9); setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3); setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3); /* It needs SW to disable core4~7 as HW design sake on T4080 */ for (i = 4; i < 8; i++) cpu_disable(i); /* request core4~7 into PH20 state, prior to entering PCL10 * state, all cores in cluster should be placed in PH20 state. */ setbits_be32(&rcpm->pcph20setr, 0xf0); /* put the 2nd cluster into PCL10 state */ setbits_be32(&rcpm->clpcl10setr, 1 << 1); } #endif if (cpu_numcores() > 1) { #ifndef CONFIG_MP puts("Unicore software on multiprocessor system!!\n" "To enable mutlticore build define CONFIG_MP\n"); #endif volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); printf("CPU%d: ", pic->whoami); } else { puts("CPU: "); } cpu = gd->arch.cpu; puts(cpu->name); if (IS_E_PROCESSOR(svr)) puts("E"); printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); printf("Core: "); switch(ver) { case PVR_VER_E500_V1: case PVR_VER_E500_V2: puts("e500"); break; case PVR_VER_E500MC: puts("e500mc"); break; case PVR_VER_E5500: puts("e5500"); break; case PVR_VER_E6500: puts("e6500"); break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); if (nr_cores > CONFIG_MAX_CPUS) { panic("\nUnexpected number of cores: %d, max is %d\n", nr_cores, CONFIG_MAX_CPUS); } get_sys_info(&sysinfo); #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK if (sysinfo.diff_sysclk == 1) puts("Single Source Clock Configuration\n"); #endif puts("Clock Configuration:"); for_each_cpu(i, core, nr_cores, mask) { if (!(i & 3)) printf ("\n "); printf("CPU%d:%-4s MHz, ", core, strmhz(buf1, sysinfo.freq_processor[core])); } #ifdef CONFIG_HETROGENOUS_CLUSTERS for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) { if (!(j & 3)) printf("\n "); printf("DSP CPU%d:%-4s MHz, ", j, strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core])); } #endif printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus)); printf("\n"); #ifdef CONFIG_FSL_CORENET if (ddr_sync == 1) { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freq_ddrbus/2), strmhz(buf2, sysinfo.freq_ddrbus)); } else { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freq_ddrbus/2), strmhz(buf2, sysinfo.freq_ddrbus)); } #else switch (ddr_ratio) { case 0x0: printf(" DDR:%-4s MHz (%s MT/s data rate), ", strmhz(buf1, sysinfo.freq_ddrbus/2), strmhz(buf2, sysinfo.freq_ddrbus)); break; case 0x7: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freq_ddrbus/2), strmhz(buf2, sysinfo.freq_ddrbus)); break; default: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freq_ddrbus/2), strmhz(buf2, sysinfo.freq_ddrbus)); break; } #endif #if defined(CONFIG_FSL_LBC) if (sysinfo.freq_localbus > LCRR_CLKDIV) { printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freq_localbus); } #endif #if defined(CONFIG_FSL_IFC) printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); #endif #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus)); #endif #ifdef CONFIG_QE printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe)); #endif #if defined(CONFIG_SYS_CPRI) printf(" "); printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri)); #endif #if defined(CONFIG_SYS_MAPLE) printf("\n "); printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple)); printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb)); printf("MAPLE-eTVPE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_maple_etvpe)); #endif #ifdef CONFIG_SYS_DPAA_FMAN for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { printf(" FMAN%d: %s MHz\n", i + 1, strmhz(buf1, sysinfo.freq_fman[i])); } #endif #ifdef CONFIG_SYS_DPAA_QBMAN printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman)); #endif #ifdef CONFIG_SYS_DPAA_PME printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme)); #endif puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n"); #ifdef CONFIG_FSL_CORENET /* Display the RCW, so that no one gets confused as to what RCW * we're actually using for this boot. */ puts("Reset Configuration Word (RCW):"); for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { u32 rcw = in_be32(&gur->rcwsr[i]); if ((i % 4) == 0) printf("\n %08x:", i * 4); printf(" %08x", rcw); } puts("\n"); #endif return 0; }