void sk3wldbg_arm::check_mode(ea_t addr) {
sel_t treg = get_segreg(addr, 20); //20 is ARM T reg
if (treg) {
debug_mode = (uc_mode)((int)UC_MODE_THUMB | (int)debug_mode);
// msg("Enabling thumb mode\n");
thumb = 1;
}
}
//--------------------------------------------------------------------------
// function to produce assume directives
void idaapi assumes(ea_t ea)
{
segreg_t *Darea = get_srarea(ea);
segment_t *Sarea = getseg(ea);
if ( Sarea == NULL || Darea == NULL || !inf.s_assume ) return;
for ( int i=ph.regFirstSreg; i <= ph.regLastSreg; i++ )
{
if ( i == ph.regCodeSreg ) continue;
sel_t now = get_segreg(ea, i);
bool show = (ea == Sarea->startEA);
if ( show || Darea->startEA == ea )
{
segreg_t *prev = get_srarea(ea-1);
if ( show || (prev != NULL && get_segreg(prev->startEA, i) != now) )
print_segment_register(i, now);
}
}
}
bool
handle_operand(const op_t &op, enum opRefType ref_type)
{
ea_t ea;
sel_t data_selector;
bool flow = true;
switch ( op.type ) {
case o_reg:
//
// Register operand.
//
//
// Nothing needs to be calculated or examined for this
// operand.
//
break;
case o_imm:
//
// Immediate operand.
//
// Make sure that this operand reference isn't a write reference.
// (Writing to an immediate value is not allowed and is a sure
// sign of a badly decoded instruction).
//
if ( ref_type == hop_WRITE ) {
//
// Attempt to write to an immediate value.
// Error.
//
warning("%a: %s,%d: bad optype %d", cmd.ea, cmd.get_canon_mnem(), op.n, op.type);
break;
}
//
// SPECIAL INSTRUCTION CASE:
//
// The LDPK instruction is decoded by ana() to have an immediate
// value as an operand. However, this immediate value is to be
// the new data page pointer, which we must track for proper
// memory referencing.
//
if ( cmd.itype == I_LDPK ) {
//
// This is an LDPK instruction. Let the kernel know that
// we are changing the current data page pointer. We track
// this bit as though it were a virtual segment register named
// I_VDS, although it is not a true register in the CPU.
//
// Determine into which data page the instruction is attempting
// to point.
//
if ( op.value == 0 ) {
//
// Data page 0 is being loaded.
//
data_selector = tms320c1x_dpage0;
} else {
//
// Data page 1 is being loaded.
//
data_selector = tms320c1x_dpage1;
}
//
// Notify the IDA kernel of the change.
//
split_srarea(
cmd.ea, // The current instruction's address
IREG_VDS, // The segment register being modified
data_selector, // The new selector value being loaded
SR_auto // How the new value was determined
);
}
//
// Let the kernel know that the instruction's address should
// be marked with a 'has immediate value' flag.
// (Useful during search?)
//
doImmd(cmd.ea);
break;
case o_phrase:
//
// Processor-specific phrase.
//
// These operands have no currently trackable side effect.
//
break;
case o_mem:
//
// Direct memory reference.
//
//
// Ask the IDA kernel for the current data page pointer selector.
//
data_selector = get_segreg(cmd.ea, IREG_VDS);
//
// Is it known?
//
if ( data_selector == BADSEL ) {
//
// The current data page pointer is unknown.
// There is nothing to do.
//
} else {
//
// The current data page pointer is known.
// Calculate the full effective address being referenced
// by this operand.
//
ea = sel2ea(data_selector) + op.addr;
//
// Generate a data cross reference from this instruction
// to the target address.
//
ua_add_dref(op.offb, ea, ref_type == hop_READ ? dr_R : dr_W);
}
//
// TODO: DMOV, ...
// These instructions read from the address in their operands
// and write to the address ADJACENT to it.
//
break;
case o_near:
//
// Code reference in current segment.
//
//
// Determine the effective address of the reference.
//
ea = toEA(cmd.cs, op.addr);
//
// Is this a 'CALL' type reference, or a branch type reference?
//
if ( InstrIsSet(cmd.itype, CF_CALL) ) {
//
// This is a CALL type reference. Make a cross reference
// that notes it.
//
ua_add_cref(op.offb, ea, fl_CN);
if ( !func_does_return(ea) )
flow = false;
} else {
//
// This is a branch type reference. Make a cross reference
// that notes it.
//
ua_add_cref(op.offb, ea, fl_JN);
}
break;
default:
//
// Unhandled operand type.
// Error.
//
warning("%a: %s,%d: bad optype %d", cmd.ea, cmd.get_canon_mnem(), op.n, op.type);
break;
}
return flow;
}
inline bool is_xy_16_bits (ea_t ea) { return (get_segreg(ea, rFx) == 0); }
inline bool is_acc_16_bits (ea_t ea) { return (get_segreg(ea, rFm) == 0); }
void sk3wldbg_aarch64::check_mode(ea_t addr) {
sel_t thumb = get_segreg(addr, 20); //20 is ARM T reg
if (thumb) {
debug_mode = (uc_mode)((int)UC_MODE_THUMB | (int)debug_mode);
}
}
//----------------------------------------------------------------------
int idaapi emu(void)
{
uint32 Feature = cmd.get_canon_feature();
flow = ((Feature & CF_STOP) == 0);
if ( Feature & CF_USE1 ) handle_operand(cmd.Op1, 1);
if ( Feature & CF_USE2 ) handle_operand(cmd.Op2, 1);
if ( Feature & CF_CHG1 ) handle_operand(cmd.Op1, 0);
if ( Feature & CF_CHG2 ) handle_operand(cmd.Op2, 0);
if ( Feature & CF_JUMP )
QueueSet(Q_jumps, cmd.ea);
if ( flow )
ua_add_cref(0,cmd.ea+cmd.size,fl_F);
uint8 code = get_byte(cmd.ea);
const struct opcode_info_t &opinfo = get_opcode_info(code);
if ( opinfo.itype == M65816_jmp || opinfo.itype == M65816_jsr )
{
if ( opinfo.addr == ABS_INDIR
|| opinfo.addr == ABS_INDIR_LONG
|| opinfo.addr == ABS_IX_INDIR )
{
QueueSet(Q_jumps,cmd.ea);
}
}
#if 0
switch ( opinfo.addr )
{
case ABS_LONG_IX:
{
ea_t orig_ea = cmd.Op1.addr;
ea_t ea = xlat(orig_ea);
bool read_access;
if ( cmd.itype == M65816_sta )
read_access = false;
else
read_access = true;
if ( !read_access )
doVar(ea);
ua_add_dref(cmd.Op1.offb, ea, read_access ? dr_R : dr_W);
break;
}
case DP:
{
bool read_access;
if ( cmd.itype == M65816_tsb || cmd.itype == M65816_asl || cmd.itype == M65816_trb
|| cmd.itype == M65816_rol || cmd.itype == M65816_lsr || cmd.itype == M65816_ror
|| cmd.itype == M65816_dec || cmd.itype == M65816_inc )
read_access = false;
else
read_access = true;
int32 val = backtrack_value(cmd.ea, 2, BT_DP);
if ( val != -1 )
{
ea_t orig_ea = val + cmd.Op1.addr;
ea_t ea = xlat(orig_ea);
ua_dodata2(cmd.Op1.offb, ea, cmd.Op1.dtyp);
if ( !read_access )
doVar(ea);
ua_add_dref(cmd.Op1.offb, ea, read_access ? dr_R : dr_W);
}
}
break;
}
#endif
switch ( cmd.itype )
{
case M65816_sep:
case M65816_rep:
{
// Switching 8 -> 16 bits modes.
uint8 flag_data = get_byte(cmd.ea + 1);
uint8 m_flag = flag_data & 0x20;
uint8 x_flag = flag_data & 0x10;
uint8 val = (cmd.itype == M65816_rep) ? 0 : 1;
if ( m_flag )
split_srarea(cmd.ea + 2, rFm, val, SR_auto);
if ( x_flag )
split_srarea(cmd.ea + 2, rFx, val, SR_auto);
}
break;
case M65816_xce:
{
// Switching to native mode?
uint8 prev = get_byte(cmd.ea - 1);
const struct opcode_info_t &opinf = get_opcode_info(prev);
if ( opinf.itype == M65816_clc )
split_srarea(cmd.ea + 1, rFe, 0, SR_auto);
else if ( opinf.itype == M65816_sec )
split_srarea(cmd.ea + 1, rFe, 1, SR_auto);
}
break;
case M65816_jmp:
case M65816_jml:
case M65816_jsl:
case M65816_jsr:
{
if ( cmd.Op1.full_target_ea )
{
ea_t ftea = cmd.Op1.full_target_ea;
if ( cmd.itype != M65816_jsl && cmd.itype != M65816_jml )
ftea = toEA(codeSeg(ftea, 0), ftea);
else
ftea = xlat(ftea);
split_srarea(ftea, rFm, get_segreg(cmd.ea, rFm), SR_auto);
split_srarea(ftea, rFx, get_segreg(cmd.ea, rFx), SR_auto);
split_srarea(ftea, rFe, get_segreg(cmd.ea, rFe), SR_auto);
split_srarea(ftea, rPB, ftea >> 16, SR_auto);
split_srarea(ftea, rB, get_segreg(cmd.ea, rB), SR_auto);
split_srarea(ftea, rDs, get_segreg(cmd.ea, rDs), SR_auto);
split_srarea(ftea, rD, get_segreg(cmd.ea, rD), SR_auto);
}
}
break;
case M65816_plb:
{
int32 val = backtrack_value(cmd.ea, 1, BT_STACK);
if ( val != -1 )
{
split_srarea(cmd.ea + cmd.size, rB, val, SR_auto);
split_srarea(cmd.ea + cmd.size, rDs, val << 12, SR_auto);
}
}
break;
case M65816_pld:
{
int32 val = backtrack_value(cmd.ea, 2, BT_STACK);
if ( val != -1 )
split_srarea(cmd.ea + cmd.size, rD, val, SR_auto);
}
break;
case M65816_plp:
{
// Ideally, should pass another parameter, specifying when to stop
// backtracking.
// For example, in order to avoid this:
// PHP
// PLP <-- this one is causing interference
// (dunno if that even happens, though)
// PLP
ea_t ea = backtrack_prev_ins(cmd.ea, M65816_php);
if ( ea != BADADDR )
{
uint16 p = get_cpu_status(ea);
split_srarea(cmd.ea + cmd.size, rFm, (p >> 5) & 0x1, SR_auto);
split_srarea(cmd.ea + cmd.size, rFx, (p >> 4) & 0x1, SR_auto);
}
}
/**
* Get what is known of the status flags register,
* at address 'ea'.
*
* ea : The effective address.
*
* returns : A 9-bit value, composed with what is known of the
* status register at the 'ea' effective address. Its
* layout is the following:
* +----------------------------------------------------------------+
* | 0 | 0 | 0 | 0 | 0 | 0 | 0 | e || n | v | m | x | d | i | z | c |
* +----------------------------------------------------------------+
* 15 7 0
* Note that a 16-bit value is returned, in order to
* take the emulation-mode flag into consideration.
*/
static uint16 get_cpu_status(ea_t ea)
{
return (get_segreg(ea, rFe) << 8) | (get_segreg(ea, rFm) << 5) | (get_segreg(ea, rFx) << 4);
}
//----------------------------------------------------------------------
static void handle_operand(op_t &x, bool read_access)
{
ea_t ea;
dref_t dreftype;
switch ( x.type )
{
case o_void:
case o_reg:
break;
case o_imm:
QASSERT(557, read_access);
dreftype = dr_O;
MAKE_IMMD:
doImmdValue();
if ( isOff(uFlag, x.n) )
ua_add_off_drefs(x, dreftype);
break;
case o_displ:
dreftype = read_access ? dr_R : dr_W;
switch ( x.phrase )
{
case rD: // "dp"
case rDX: // "dp, X"
case rDY: // "dp, Y"
case riDX: // "(dp, X)"
case rDi: // "(dp,n)"
case rDiL: // "long(dp,n)"
case rDiY: // "(dp,n), Y"
case rDiLY: // "long(dp,n), Y"
{
sel_t dp = get_segreg(cmd.ea, rD);
if ( dp != BADSEL )
{
ea_t orig_ea = dp + x.addr;
ea = xlat(orig_ea);
goto MAKE_DREF;
}
else
{
goto MAKE_IMMD;
}
}
case rAbsi: // "(abs)"
case rAbsX: // "abs, X"
case rAbsY: // "abs, Y"
case rAbsiL: // "long(abs)"
ea = toEA(dataSeg_op(x.n), x.addr);
goto MAKE_DREF;
case rAbsXi: // "(abs,X)"
ea = toEA(codeSeg(cmd.ea, x.n), x.addr); // jmp, jsr
goto MAKE_DREF;
case rAbsLX: // "long abs, X"
ea = x.addr;
goto MAKE_DREF;
default:
goto MAKE_IMMD;
}
case o_mem:
case o_mem_far:
ea = calc_addr(x);
MAKE_DREF:
ua_dodata2(x.offb, ea, x.dtyp);
if ( !read_access )
doVar(ea);
ua_add_dref(x.offb, ea, read_access ? dr_R : dr_W);
break;
case o_near:
case o_far:
{
ea_t orig_ea;
ea = calc_addr(x, &orig_ea);
if ( cmd.itype == M65816_per )
{
ua_add_dref(x.offb, ea, dr_O);
}
else
{
bool iscall = InstrIsSet(cmd.itype, CF_CALL);
cref_t creftype = x.type == o_near
? iscall ? fl_CN : fl_JN
: iscall ? fl_CF : fl_JF;
ua_add_cref(x.offb, ea, creftype);
if ( flow && iscall )
flow = func_does_return(ea);
}
}
break;
default:
INTERR(558);
}
}
