static int __init config_init(void)
{
struct timespec init_time,init_time1,init_time2;
unsigned long diff;
struct timespec current_time;
int flag1=-1,flag2=-1;
unsigned long long initial_clock,current_clock;
getrawmonotonic(&init_time1);
getrawmonotonic(&init_time2);
// printk("%ld\n",init_time2.tv_nsec-init_time1.tv_nsec);
// initial_clock=trace_clock_counter();
getrawmonotonic(&init_time);
getrawmonotonic(¤t_time);
diff=current_time.tv_sec-init_time.tv_sec;
//printk("difference %ld\n",diff);
while(diff<10)
{
//printk("%ld\n",diff);
flag2=diff;
if(flag1!=flag2)
{
printk("%d\n",diff);
flag1=flag2;
}
getrawmonotonic(¤t_time);
diff=current_time.tv_sec-init_time.tv_sec;
// current_clock=trace_clock_counter();
// printk("timediff %ld %ld\n",current_time.tv_sec-init_time.tv_sec,current_time.tv_nsec-init_time.tv_nsec);//,current_time->tv_nsec-init_time->tv_nsec);
}
return 0;
}
/**
* ktime_get_raw - Returns the raw monotonic time in ktime_t format
*/
ktime_t ktime_get_raw(void)
{
struct timespec ts;
getrawmonotonic(&ts);
return timespec_to_ktime(ts);
}
irqreturn_t stml0xx_wake_isr(int irq, void *dev)
{
static struct timespec ts;
static struct stml0xx_work_struct *stm_ws;
struct stml0xx_data *ps_stml0xx = dev;
getrawmonotonic(&ts);
if (stml0xx_irq_disable)
return IRQ_HANDLED;
wake_lock_timeout(&ps_stml0xx->wake_sensor_wakelock, HZ);
stm_ws = kmalloc(
sizeof(struct stml0xx_work_struct),
GFP_ATOMIC);
if (!stm_ws) {
dev_err(dev, "stml0xx_wake_isr: unable to allocate work struct");
return IRQ_HANDLED;
}
INIT_WORK((struct work_struct *)stm_ws, stml0xx_irq_wake_work_func);
stm_ws->ts_ns = ts_to_ns(ts);
queue_work(ps_stml0xx->irq_work_queue, (struct work_struct *)stm_ws);
return IRQ_HANDLED;
}
static long kfd_ioctl_get_clock_counters(struct file *filep,
struct kfd_process *p, void __user *arg)
{
struct kfd_ioctl_get_clock_counters_args args;
struct kfd_dev *dev;
struct timespec time;
if (copy_from_user(&args, arg, sizeof(args)))
return -EFAULT;
dev = kfd_device_by_id(args.gpu_id);
if (dev == NULL)
return -EINVAL;
/* Reading GPU clock counter from KGD */
args.gpu_clock_counter = kfd2kgd->get_gpu_clock_counter(dev->kgd);
/* No access to rdtsc. Using raw monotonic time */
getrawmonotonic(&time);
args.cpu_clock_counter = (uint64_t)timespec_to_ns(&time);
get_monotonic_boottime(&time);
args.system_clock_counter = (uint64_t)timespec_to_ns(&time);
/* Since the counter is in nano-seconds we use 1GHz frequency */
args.system_clock_freq = 1000000000;
if (copy_to_user(arg, &args, sizeof(args)))
return -EFAULT;
return 0;
}
u32 b2r2_get_curr_nsec(void)
{
struct timespec ts;
getrawmonotonic(&ts);
return (u32)timespec_to_ns(&ts);
}
/*
* Initialize the battery cell state structure,
* Setup initial parameters and timers
* NOTE: make sure *cell is 0-filled!
*/
void fg_init(struct cell_state *cell, short voltage, short temperature)
{
unsigned short i;
struct timespec ts;
cell->fcc = cell->config->design_capacity;
cell->qmax = cell->config->design_qmax;
cell->new_fcc = cell->fcc;
cell->voltage = voltage;
cell->prev_voltage = voltage;
cell->av_voltage = voltage;
for (i = 0; i < AV_SIZE; i++) {
av_v[i] = voltage;
av_c[i] = 0;
}
av_v_index = 0;
av_c_index = 0;
/*Check for faulty temperature sensor error. Valid operating temerature range -40 to +60 degC */
if(temperature < -400 || temperature > 600 )
{
dev_dbg(cell->dev, "Battery temperature overrange (%d) using room temperature as default. \n", temperature);
cell->temperature = 250; /* 25C room temperature */
}
else
{
cell->temperature = temperature;
}
/* On init, by-pass temperature debounce check */
cell->seq_cc_temperature = FG_TEMP_CHANGE_COUNT;
cell->cycle_count = 1;
#ifdef CONFIG_JET_V2
cell->temp_index = -1;
cell->current_bounce_counter=0;
#endif
cell->learned_cycle = cell->cycle_count;
cell->prev_soc = -1;
/*On init, get correct EDV table from temperature compensation*/
fg_temperature_compensate(cell);
/* On init, get SOC from OCV */
fg_ocv(cell);
printk(KERN_INFO "FG: Init (%dv, %dmAh, %d%%, %dC)\n", voltage, cell->nac, cell->soc, cell->temperature/10);
/* Update EDV flags */
fg_update_edv_flags(cell, true);
getrawmonotonic(&ts);
cell->last_correction.tv_sec = ts.tv_sec;
cell->init = true;
}
static __init int start_module(void)
{
dev=name_to_dev_t(device);
disk = get_gendisk(dev,&dummy);
if(!disk)
return 0;
queue=disk->queue;
getrawmonotonic(&init_time);
block_fun=my_block_fun;
block_requeue=my_block_requeue;
block_comp=my_block_comp;
return 0;
}
static irqreturn_t cc2520_sfd_handler(int irq, void *dev_id)
{
int gpio_val;
struct timespec ts;
s64 nanos;
// NOTE: For now we're assuming no delay between SFD called
// and actual SFD received. The TinyOS implementations call
// for a few uS of delay, but it's likely not needed.
getrawmonotonic(&ts);
nanos = timespec_to_ns(&ts);
gpio_val = gpio_get_value(CC2520_SFD);
DBG((KERN_INFO "[cc2520] - sfd interrupt occurred at %lld, %d\n", (long long int)nanos, gpio_val));
cc2520_radio_sfd_occurred(nanos, gpio_val);
return IRQ_HANDLED;
}
void tl_select_relay(struct tr_info_list *list){
struct timespec tl_diff;
getrawmonotonic(&tl_end);
tl_diff = timespec_sub(tl_end, tl_start);
//printk("Topology learning time: %ld\n", timespec_to_ns(&tl_diff));
if(list == NULL){
printk("Select Relay error1\n");
return;
}
if(list->next == NULL){
printk("Select Relay error2\n");
return;
}
tr_info_list_arrangement(list);
if(MNPRELAY) mnp_relay(list);
else min_max_relay(list);
}
static void my_block_fun(struct task_struct *task,struct bio* bio)
{
getrawmonotonic(¤t_time);
if(strcmp(disk->disk_name,bio->bi_bdev->bd_disk->disk_name)==0)
{
seq++;
RW=(bio->bi_rw)?'R':'W';
F=(task->bio_list)?'M':'I';
sector=(bio->bi_io_vec->bv_offset);
size=bio_sectors(bio);
cpu=task_thread_info(task)->cpu;
diff_sec=current_time.tv_sec-init_time.tv_sec;
diff_nsec=current_time.tv_nsec-init_time.tv_nsec;
printk("%d,%d %d %ld %ld.%ld %d %c %c %lld+%d %s\n",MAJOR(dev),MINOR(dev),cpu,seq,diff_sec,diff_nsec,task->pid,F,RW,sector,size,task->comm);
}
if((current_time.tv_sec-init_time.tv_sec)>timer)
{
block_fun=NULL;
block_requeue=NULL;
block_comp=NULL;
}
}
/* Checks for right conditions for OCV correction */
static bool fg_can_ocv(struct cell_state *cell)
{
struct timespec now;
int tmp;
getrawmonotonic(&now);
tmp = now.tv_sec - cell->last_ocv.tv_sec;
/* Don't do OCV to often */
if ((tmp < cell->config->ocv->ocv_period) && cell->init)
return false;
/* Voltage should be stable */
if (cell->config->ocv->voltage_diff <= diff_array(av_v, AV_SIZE))
return false;
/* Current should be stable */
if (cell->config->ocv->current_diff <= diff_array(av_c, AV_SIZE))
return false;
/* SOC should be out of Flat Zone */
if ((cell->soc >= cell->config->ocv->flat_zone_low) &&
(cell->soc <= cell->config->ocv->flat_zone_high))
return false;
/* Current should be less then SleepEnterCurrent */
if (abs(cell->cur) >= cell->config->ocv->sleep_enter_current)
return false;
/* Don't allow OCV below EDV1, unless OCVbelowEDV1 is set */
if (cell->edv1 && !cell->config->ocv_below_edv1)
return false;
#ifdef CONFIG_POWER_SUPPLY_DEBUG
printk(KERN_DEBUG "%s\n",__func__);
#endif
return true;
}
void kbase_backend_get_gpu_time(struct kbase_device *kbdev, u64 *cycle_counter,
u64 *system_time, struct timespec *ts)
{
u32 hi1, hi2;
kbase_pm_request_gpu_cycle_counter(kbdev);
/* Read hi, lo, hi to ensure that overflow from lo to hi is handled
* correctly */
do {
hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI),
NULL);
*cycle_counter = kbase_reg_read(kbdev,
GPU_CONTROL_REG(CYCLE_COUNT_LO), NULL);
hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI),
NULL);
*cycle_counter |= (((u64) hi1) << 32);
} while (hi1 != hi2);
/* Read hi, lo, hi to ensure that overflow from lo to hi is handled
* correctly */
do {
hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_HI),
NULL);
*system_time = kbase_reg_read(kbdev,
GPU_CONTROL_REG(TIMESTAMP_LO), NULL);
hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_HI),
NULL);
*system_time |= (((u64) hi1) << 32);
} while (hi1 != hi2);
/* Record the CPU's idea of current time */
getrawmonotonic(ts);
kbase_pm_release_gpu_cycle_counter(kbdev);
}
/* Main FG entry point. This function needs to be called periodically.*/
void fg_process(struct cell_state *cell, short delta_q, short raw_voltage, short norm_voltage,
short cur, short temperature)
{
int i, tmp;
struct timespec now;
if (!cell->init)
return;
/* Update voltage and add it to the buffer, update average*/
tmp = 0;
cell->voltage = norm_voltage;
av_v_index++;
av_v_index %= AV_SIZE;
av_v[av_v_index] = norm_voltage;
for (i = 0; i < AV_SIZE; i++) {
tmp += av_v[i];
}
cell->av_voltage = tmp/AV_SIZE;
/* Update current and add it to the buffer, update average*/
tmp = 0;
cell->cur = cur;
av_c_index++;
av_c_index %= AV_SIZE;
av_c[av_c_index] = cur;
for (i = 0; i < AV_SIZE; i++)
tmp += av_c[i];
cell->av_current = tmp/AV_SIZE;
/* Update temperature*/
cell->temperature = temperature;
/*Update FCC and EDV table from temperature compensation*/
fg_temperature_compensate(cell);
/* Check time since last_call */
getrawmonotonic(&now);
tmp = now.tv_sec - cell->last_correction.tv_sec;
/* Check what capacity correction algorithm should we use: OCV or CC */
if ((tmp > cell->config->ocv->relax_period) &&
(abs(cell->cur) < cell->config->ocv->long_sleep_current)) {
#ifdef CONFIG_POWER_SUPPLY_DEBUG
printk(KERN_DEBUG "OCV check 1\n");
#endif
fg_ocv(cell);
} else if (fg_check_relaxed(cell)) {
/* We are not doing any active CHG/DSG, clear flags
this does not compromise learning cycles */
cell->chg = false;
cell->dsg = false;
/* Checking if we can do an OCV correction */
if (fg_can_ocv(cell))
fg_ocv(cell);
else
fg_cc(cell, delta_q);
} else /* Not Relaxed: actively charging or discharging */
fg_cc(cell, delta_q);
/* Charge / Discharge spesific functionality */
if (!cell->sleep) {
if (cell->cur > 0)
fg_charging(cell, delta_q);
else if (cell->cur < 0)
fg_discharging(cell, delta_q);
}
/* Update Regular SOC */
cell->soc = DIV_ROUND_CLOSEST(cell->nac * MAX_PERCENTAGE, cell->fcc);
/* The voltage will vibrate a lot when close to shutdown voltage. This happens especially when running high power
* consumption app. So need to take care of the end check
*/
/*Add here to check both nac and EDV0*/
if(cell->soc > EDV_FIRST_CHECK_POINT+5){
fg_ocv_check(cell);
}
else if(cell->soc==0){
#ifdef BATTERY_DRAIN_CONFIG
cell->soc=1;
#else
fg_check_end(cell);
#endif
}
/* When SOC is below 15%, check if raw voltage level reached hardware shutdown threshold */
if(cell->soc < EDV_FIRST_CHECK_POINT+5){
fg_check_shutdown_voltage(cell, raw_voltage);
}
fg_update_edv_flags(cell, false);
/* Check if battery is full */
if (cell->cc) {
cell->full = true;
}
if (cell->soc < MAX_PERCENTAGE) {
cell->full = false;
if (cell->nac <= (cell->fcc - cell->config->recharge))
cell->cc = false;
}
/* Check if SOC reached 100% and battery is still charging, then keep SOC at 99% */
if((*cell->charge_status == POWER_SUPPLY_STATUS_CHARGING) &&
(cell->soc == MAX_PERCENTAGE) && !cell->cc && !cell->full)
{
#ifdef DEBUG
printk(KERN_DEBUG "End of charge not reach yet\n");
#endif
cell->soc = MAX_PERCENTAGE-1;
}
/* Checking if we need to set an updated flag (is SOC changed) */
if (cell->prev_soc != cell->soc) {
cell->prev_soc = cell->soc;
cell->updated = true;
}
cell->last_correction.tv_sec = now.tv_sec;
#if 0
//JET-376 test, run calibration every 5-min to check cc_offset value
cal_cntr++;
if(cal_cntr >= 30)
{
cell->calibrate = true;
cal_cntr = 0;
printk(KERN_DEBUG "PMIC Calibrate now! \n");
}
#endif
#ifdef DEBUG
/* Printing Debug Data */
printk(KERN_DEBUG
"FG:ACC:%2d; RM:%4d,mAh; SOC:%3d%%; VOLT:%4d,%4d,mV; "
"CUR:%5d,%5d,mA; TEMP:%3d; "
"EDV:%d,mV,%02d%%; "
"LLL:%4d,%4d,%4d; "
"N/O:%4d,%4d; "
"CS:%4d; EL:%5d; "
"FCC:%d,%d; CP:%d; \n",
delta_q, cell->nac, cell->soc, cell->voltage, cell->av_voltage,
cell->cur, cell->av_current, cell->temperature,
cell->edv.voltage, cell->edv.percent,
cell->learn_q, cell->learn_offset, cell->ocv_total_q,
cell->negative_q, cell->overcharge_q,
cell->cumulative_sleep, cell->electronics_load,
cell->fcc, cell->cycle_count, tmp);
print_flags(cell);
#endif
}
// time in us
static u64 medusa_time(void)
{
struct timespec now;
getrawmonotonic(&now);
return (u64)now.tv_sec * USEC_PER_SEC + (u64)(now.tv_nsec / NSEC_PER_USEC);
}
/*
* Get monotonic-raw time for posix timers
*/
static int posix_get_monotonic_raw(clockid_t which_clock, struct timespec *tp)
{
getrawmonotonic(tp);
return 0;
}
static inline unsigned long long monotonic_clock(void)
{
struct timespec ts;
getrawmonotonic(&ts);
return timespec_to_ns(&ts);
}
/*
* Each ring entry is 128 bits:
* [7:0] - interrupt source id
* [31:8] - reserved
* [59:32] - interrupt source data
* [63:60] - reserved
* [71:64] - RINGID
* [79:72] - VMID
* [127:80] - reserved
*/
static void vector(struct pci_dev *dev, u32 id, u32 data, u8 ring_id,
u8 *irq_thd, u8 *dce6_irqs_acked)
{
struct dev_drv_data *dd;
dd = pci_get_drvdata(dev);
switch (id) {
case VECTOR_ID_HPD:
if (!*dce6_irqs_acked) {
dce6_irqs_ack(dd->dce);
*dce6_irqs_acked = 1;
}
dce6_hpd_irq(dd->dce, data);
*irq_thd = IRQ_THD_ENA;
break;
case VECTOR_ID_D0:
case VECTOR_ID_D1:
case VECTOR_ID_D2:
case VECTOR_ID_D3:
case VECTOR_ID_D4:
case VECTOR_ID_D5:
if (!*dce6_irqs_acked) {
dce6_irqs_ack(dd->dce);
*dce6_irqs_acked = 1;
}
if (data == Dx_VBLANK) {/* only page flipping in vblank */
struct timespec tp;
getrawmonotonic(&tp);
dce6_pf_irq(dd->dce, id - 1, tp);
}
break;
case VECTOR_ID_EOP:
switch(ring_id) {
case 0:
atomic_set(&dd->gpu_3d.fence.bottom,
le32_to_cpup(dd->gpu_3d.fence.cpu_addr));
wake_up(&dd->gpu_3d.fence.wait_queue);
break;
case 1:
atomic_set(&dd->gpu_c0.fence.bottom,
le32_to_cpup(dd->gpu_c0.fence.cpu_addr));
wake_up(&dd->gpu_c0.fence.wait_queue);
break;
case 2:
atomic_set(&dd->gpu_c1.fence.bottom,
le32_to_cpup(dd->gpu_c1.fence.cpu_addr));
wake_up(&dd->gpu_c1.fence.wait_queue);
break;
};
break;
case VECTOR_ID_DMA_0:
atomic_set(&dd->dmas[0].fence.bottom,
le32_to_cpup(dd->dmas[0].fence.cpu_addr));
wake_up(&dd->dmas[0].fence.wait_queue);
break;
case VECTOR_ID_DMA_1:
atomic_set(&dd->dmas[1].fence.bottom,
le32_to_cpup(dd->dmas[1].fence.cpu_addr));
wake_up(&dd->dmas[1].fence.wait_queue);
break;
}
}
void tl_start_time(){
getrawmonotonic(&tl_start);
}
