void up_enable_irq(int irq)
{
/* Enable the interrupt by setting the corresponding bit in
* the IRQ enable register.
*/
if (irq < 16)
{
/* IRQs0-15 are controlled by the IRQ0 enable register
* Set the associated bit to enable the interrupt
*/
putreg16((getreg16(DM320_INTC_EINT0) | (1 << irq)), DM320_INTC_EINT0);
}
else if (irq < 32)
{
/* IRQs16-31 are controlled by the IRQ1 enable register
* Set the associated bit to enable the interrupt
*/
putreg16((getreg16(DM320_INTC_EINT1) | (1 << (irq-16))), DM320_INTC_EINT1);
}
else
{
/* IRQs32- are controlled by the IRQ2 enable register
* Set the associated bit to enable the interrupt
*/
putreg16((getreg16(DM320_INTC_EINT2) | (1 << (irq-32))), DM320_INTC_EINT2);
}
}
static void dm320_disable(void)
{
/* Disable all planes */
gvdbg("Inactivate OSD:\n");
putreg16(0, DM320_OSD_OSDWIN0MD); /* Win0 mode = 0 (1:active) */
putreg16(0, DM320_OSD_OSDWIN1MD); /* Win1 mode = 0 (1:active) */
putreg16(0, DM320_OSD_RECTCUR); /* Rectangular cursor mode = 0 (1:active) */
gvdbg("DM320_OSD_OSDWIN0MD: %04x\n", getreg16(DM320_OSD_OSDWIN0MD));
gvdbg("DM320_OSD_OSDWIN1MD: %04x\n", getreg16(DM320_OSD_OSDWIN1MD));
gvdbg("DM320_OSD_RECTCUR: %04x\n", getreg16(DM320_OSD_RECTCUR));
}
static int dm320_putcmap(FAR struct fb_vtable_s *vtable, FAR struct fb_cmap_s *cmap)
{
irqstate_t flags;
uint16_t regval;
uint8_t y;
uint8_t u;
uint8_t v;
int len
int i;
#ifdef CONFIG_DEBUG
if (!vtable || !cmap || !cmap->read || !cmap->green || !cmap->blue)
{
return -EINVAL;
}
#endif
flags = enter_critical_section();
for (i = cmap.first, len = 0; i < 256 && len < cmap.len, i++, len++)
{
/* Convert the RGB to YUV */
nxgl_rgb2yuv(cmap->red[i], cmap->green[i], cmap->blue[i], &y, &u, &v);
/* Program the CLUT */
while (getreg16(DM320_OSD_MISCCTL) & 0x8);
putreg16(((uint16_t)y) << 8 | uint16_t(u)), DM320_OSD_CLUTRAMYCB);
putreg16(((uint16_t)v << 8 | i), DM320_OSD_CLUTRAMCR);
}
/* Select RAM clut */
#if !defined(CONFIG_DM320_OSD0_DISABLE) && !defined(CONFIG_DM320_OSD0_RGB16)
regval = getreg16(DM320_OSD_OSDWIN0MD);
regval |= 0x1000;
putreg16(regval, DM320_OSD_OSDWIN0MD);
#endif
#if !defined(CONFIG_DM320_OSD1_DISABLE) && !defined(CONFIG_DM320_OSD1_RGB16)
regval = getreg16(DM320_OSD_OSDWIN1MD);
regval |= 0x1000;
putreg16(regval, DM320_OSD_OSDWIN1MD);
#endif
leave_critical_section(flags);
return 0;
}
uint8_t board_buttons(void)
{
uint8_t ret = 0;
if ((getreg16(STR71X_GPIO0_PD) & STR71X_WAKEUPBUTTON_GPIO0) != 0)
{
ret |= WAKEUP_BUTTON;
}
if ((getreg16(STR71X_GPIO1_PD) & STR71X_BUTBUTTON_GPIO1) != 0)
{
ret |= BUT_BUTTON;
}
return ret;
}
static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords)
{
FAR uint8_t *ptr = (FAR uint8_t*)buffer;
uint32_t rxpending = 0;
/* While there is remaining to be sent (and no synchronization error has occurred) */
spidbg("nwords: %d\n", nwords);
while (nwords || rxpending)
{
/* Fill the transmit FIFO with 0xff...
* Write 0xff to the data register while (1) the TX FIFO is
* not full, (2) we have not exceeded the depth of the TX FIFO,
* and (3) there are more bytes to be sent.
*/
spivdbg("TX: rxpending: %d nwords: %d\n", rxpending, nwords);
while ((getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_TNF) &&
(rxpending < LPC214X_SPI1_FIFOSZ) && nwords)
{
putreg16(0xff, LPC214X_SPI1_DR);
nwords--;
rxpending++;
}
/* Now, read the RX data from the RX FIFO while the RX FIFO is not empty */
spivdbg("RX: rxpending: %d\n", rxpending);
while (getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_RNE)
{
*ptr++ = (uint8_t)getreg16(LPC214X_SPI1_DR);
rxpending--;
}
}
}
static void set_default_priorities(void)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(default_irq_prio); i++)
{
uint16_t val;
uint8_t prio = default_irq_prio[i];
if (prio > 31)
{
prio = 31;
}
val = getreg16(IRQ_REG(ILR_IRQ(i)));
val &= ~(0x1f << 2);
val |= prio << 2;
/* Make edge mode default. Hopefully causes less trouble */
val |= 0x02;
putreg16(val, IRQ_REG(ILR_IRQ(i)));
}
}
int uwire_xfer(int cs, int bitlen, const void *dout, void *din)
{
uint16_t tmp = 0;
if (bitlen <= 0 || bitlen > 16)
return -1;
if (cs < 0 || cs > 4)
return -1;
/* FIXME uwire_init always selects CS0 for now */
dbg("uwire_xfer(dev_idx=%u, bitlen=%u\n", cs, bitlen);
/* select the chip */
putreg16(UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD, UWIRE_REG(REG_CSR));
_uwire_wait(UWIRE_CSR_CSRB, 0);
if (dout)
{
if (bitlen <= 8)
tmp = *(uint8_t *)dout;
else if (bitlen <= 16)
tmp = *(uint16_t *)dout;
tmp <<= 16 - bitlen; /* align to MSB */
putreg16(tmp, UWIRE_REG(REG_DATA));
dbg(", data_out=0x%04hx", tmp);
}
tmp = (dout ? UWIRE_CSR_BITS_WR(bitlen) : 0) |
(din ? UWIRE_CSR_BITS_RD(bitlen) : 0) |
UWIRE_CSR_START;
putreg16(tmp, UWIRE_REG(REG_CSR));
_uwire_wait(UWIRE_CSR_CSRB, 0);
if (din)
{
_uwire_wait(UWIRE_CSR_RDRB, UWIRE_CSR_RDRB);
tmp = getreg16(UWIRE_REG(REG_DATA));
dbg(", data_in=0x%08x", tmp);
if (bitlen <= 8)
*(uint8_t *)din = tmp & 0xff;
else if (bitlen <= 16)
*(uint16_t *)din = tmp & 0xffff;
}
/* unselect the chip */
putreg16(UWIRE_CSR_IDX(0) | 0, UWIRE_REG(REG_CSR));
_uwire_wait(UWIRE_CSR_CSRB, 0);
dbg(")\n");
return 0;
}
static void stm32_ili93414ws_spidisable(void)
{
uint16_t regval;
regval = getreg16(ILI93414WS_SPI_CR1);
regval &= ~SPI_CR1_SPE;
putreg16(regval, ILI93414WS_SPI_CR1);
}
static uint16_t cs89x0_getreg(struct cs89x0_driver_s *cs89x0, int offset)
{
#ifdef CONFIG_CS89x0_ALIGN16
return getreg16(s89x0->cs_base + offset);
#else
return (uint16_t)getreg32(s89x0->cs_base + offset);
#endif
}
static int lcd_setpower(struct lcd_dev_s *dev, int power)
{
uint16_t reg;
if (g_lcddev.power == power) {
return OK;
}
ginfo("power: %d\n", power);
DEBUGASSERT(power <= CONFIG_LCD_MAXPOWER);
/* Set new power level */
reg = getreg16(ASIC_CONF_REG);
if (power)
{
reg = getreg16(ASIC_CONF_REG);
/* LCD Set I/O(3) / SA0 to I/O(3) mode */
reg &= ~( (1 << 12) | (1 << 10) | (1 << 7) | (1 << 1)) ;
/* don't set function pins to I2C Mode, C155 uses UWire */
/* TWL3025: Set SPI+RIF RX clock to rising edge */
reg |= (1 << 13) | (1 << 14);
putreg16(reg, ASIC_CONF_REG);
/* LCD Set I/O(3) to output mode and enable C155 backlight (IO1) */
/* FIXME: Put the display backlight control to backlight.c */
reg = getreg16(IO_CNTL_REG);
reg &= ~( (1 << 3) | (1 << 1));
putreg16(reg, IO_CNTL_REG);
/* LCD Set I/O(3) output low */
reg = getreg16(ARMIO_LATCH_OUT);
reg &= ~(1 << 3);
reg |= (1 << 1);
putreg16(reg, ARMIO_LATCH_OUT);
}
else
{
ginfo("powering LCD off...\n");
/* Switch pin from PWL to LT */
reg &= ~ASCONF_PWL_ENA;
putreg8(reg, ASIC_CONF_REG);
/* Disable pwl */
putreg8(0x00, PWL_REG(PWL_CTRL));
}
return OK;
}
void z16f_sysexec(FAR chipreg_t *regs)
{
uint16_t excp;
/* Save that register reference so that it can be used for built-in
* diagnostics.
*/
current_regs = regs;
/* The cause of the system exception is indicated in the SYSEXCPH&L
* registers
*/
excp = getreg16(Z16F_SYSEXCP);
if ((excp & Z16F_SYSEXCP_SPOVF) != 0)
{
SYSDBG("SP OVERFLOW\n");
}
if ((excp & Z16F_SYSEXCP_PCOVF) != 0)
{
SYSDBG("PC OVERFLOW\n");
}
if ((excp & Z16F_SYSEXCP_DIV0) != 0)
{
SYSDBG("Divide by zero\n");
}
if ((excp & Z16F_SYSEXCP_DIVOVF) != 0)
{
SYSDBG("Divide overflow\n");
}
if ((excp & Z16F_SYSEXCP_ILL) != 0)
{
SYSDBG("Illegal instruction\n");
}
if ((excp & Z16F_SYSEXCP_WDTOSC) != 0)
{
SYSDBG("WDT oscillator failure\n");
}
if ((excp & Z16F_SYSEXCP_PRIOSC) != 0)
{
SYSDBG("Primary Oscillator Failure\n");
}
if ((excp & Z16F_SYSEXCP_WDT) != 0)
{
SYSDBG("Watchdog timeout\n");
z16f_reset();
}
PANIC();
}
static int dm320_getcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_cursorattrib_s *attrib)
{
irqstate_t flags;
#ifdef CONFIG_DEBUG
if (!vtable || !attrib)
{
return -EINVAL;
}
#endif
flags = enter_critical_section();
attrib->pos.x = getreg16(DM320_OSD_CURXP);
attrib->pos.y = getreg16(DM320_OSD_CURYP);
#ifdef CONFIG_FB_HWCURSORSIZE
attrib->size.w = getreg16(DM320_OSD_CURXL);
attrib->size.h = getreg16(DM320_OSD_CURYL);
#endif
leave_critical_section(flags);
attrib->mxsize.w = MAX_XRES;
attrib->mxsize.h = MAX_YRES;
gvdbg("DM320_OSD_CURXP: %04x\n", attrib->pos.x);
gvdbg("DM320_OSD_CURYP: %04x\n", attrib->pos.y);
#ifdef CONFIG_FB_HWCURSORSIZE
gvdbg("DM320_OSD_CURXL: %04x\n", attrib->size.w);
gvdbg("DM320_OSD_CURYL: %04x\n", attrib->size.h);
#else
gvdbg("DM320_OSD_CURXL: %04x\n", getreg16(DM320_OSD_CURXL));
gvdbg("DM320_OSD_CURYL: %04x\n", getreg16(DM320_OSD_CURYL));
#endif
gvdbg("DM320_OSD_RECTCUR: %04x\n", getreg16(DM320_OSD_RECTCUR));
}
uint16_t hwtimer_read(int num)
{
uint8_t ctl = getreg8(TIMER_REG(num, CNTL_TIMER));
/* somehow a read results in an abort */
if ((ctl & (CNTL_START|CNTL_CLOCK_ENABLE)) != (CNTL_START|CNTL_CLOCK_ENABLE))
return 0xFFFF;
return getreg16(TIMER_REG(num, READ_TIMER));
}
static void stm32_ili93414ws_modifyreg(uint32_t reg, uint16_t setbits,
uint16_t clrbits)
{
uint16_t regval;
regval = getreg16(reg);
regval &= ~clrbits;
regval |= setbits;
putreg16(regval, reg);
}
static void stm32_ili93414ws_sndword(uint16_t wd)
{
/* Send the word */
putreg16(wd, ILI93414WS_SPI_DR);
/* Wait until the transmit buffer is empty */
while ((getreg16(ILI93414WS_SPI_SR) & SPI_SR_TXE) == 0);
}
void up_lowsetup(void)
{
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
uint16_t reg16;
/* Enable the selected console device */
/* Set the UART baud rate */
putreg16((uint16_t)UART_BAUDRATE, STR71X_UART_BR(STR71X_UART_BASE));
/* Configure the UART control registers */
putreg16(STR71X_UARTCR_VALUE, STR71X_UART_CR(STR71X_UART_BASE));
/* Clear FIFOs */
putreg16(0, STR71X_UART_TXRSTR(STR71X_UART_BASE));
putreg16(0, STR71X_UART_RXRSTR(STR71X_UART_BASE));
#endif
/* Configure GPIO0 pins to enable all UARTs in the configuration
* (the serial driver later depends on this configuration)
*/
#ifdef HAVE_UART
reg16 = getreg16(STR71X_GPIO0_PC0);
reg16 &= ~STR71X_UART_GPIO0_MASK;
reg16 |= STR71X_UART_GPIO0_PC0BITS;
putreg16(reg16, STR71X_GPIO0_PC0);
reg16 = getreg16(STR71X_GPIO0_PC1);
reg16 &= ~STR71X_UART_GPIO0_MASK;
reg16 |= STR71X_UART_GPIO0_PC1BITS;
putreg16(reg16, STR71X_GPIO0_PC1);
reg16 = getreg16(STR71X_GPIO0_PC2);
reg16 &= ~STR71X_UART_GPIO0_MASK;
reg16 |= STR71X_UART_GPIO0_PC2BITS;
putreg16(reg16, STR71X_GPIO0_PC2);
#endif
}
void up_decodeirq(uint32_t* regs)
{
#ifdef CONFIG_SUPPRESS_INTERRUPTS
lowsyslog("Unexpected IRQ\n");
current_regs = regs;
PANIC();
#else
/* Decode the interrupt. First, fetch the interrupt id register. */
uint16_t irqentry = getreg16(DM320_INTC_IRQENTRY0);
/* The irqentry value is an offset into a table. Zero means no interrupt. */
if (irqentry != 0)
{
/* If non-zero, then we can map the table offset into an IRQ number */
int irq = (irqentry >> 2) - 1;
/* Verify that the resulting IRQ number is valid */
if ((unsigned)irq < NR_IRQS)
{
uint32_t *savestate;
/* Mask and acknowledge the interrupt */
up_maskack_irq(irq);
/* Current regs non-zero indicates that we are processing an interrupt;
* current_regs is also used to manage interrupt level context switches.
*/
savestate = (uint32_t*)current_regs;
current_regs = regs;
/* Deliver the IRQ */
irq_dispatch(irq, regs);
/* Restore the previous value of current_regs. NULL would indicate that
* we are no longer in an interrupt handler. It will be non-NULL if we
* are returning from a nested interrupt.
*/
current_regs = savestate;
/* Unmask the last interrupt (global interrupts are still
* disabled).
*/
up_enable_irq(irq);
}
}
void up_lowputc(char ch)
{
#ifdef HAVE_CONSOLE
/* Wait until the TX FIFO is not full */
while ((getreg16(STR71X_UART_SR(STR71X_UART_BASE)) & STR71X_UARTSR_TF) != 0);
/* Then send the character */
putreg16((uint16_t)ch, STR71X_UART_TXBUFR(STR71X_UART_BASE));
#endif
}
void board_button_initialize(void)
{
uint16_t reg16;
/* Configure the GPIO0 & 1 pins as inputs */
reg16 = getreg16(STR71X_GPIO0_PC0);
reg16 |= STR71X_WAKEUPBUTTON_GPIO0;
putreg16(reg16, STR71X_GPIO0_PC0);
reg16 = getreg16(STR71X_GPIO0_PC1);
reg16 &= ~STR71X_WAKEUPBUTTON_GPIO0;
putreg16(reg16, STR71X_GPIO0_PC1);
reg16 = getreg16(STR71X_GPIO0_PC2);
reg16 &= ~STR71X_WAKEUPBUTTON_GPIO0;
putreg16(reg16, STR71X_GPIO0_PC2);
reg16 = getreg16(STR71X_GPIO1_PC0);
reg16 |= STR71X_BUTBUTTON_GPIO1;
putreg16(reg16, STR71X_GPIO1_PC0);
reg16 = getreg16(STR71X_GPIO1_PC1);
reg16 &= ~STR71X_BUTBUTTON_GPIO1;
putreg16(reg16, STR71X_GPIO1_PC1);
reg16 = getreg16(STR71X_GPIO1_PC2);
reg16 &= ~STR71X_BUTBUTTON_GPIO1;
putreg16(reg16, STR71X_GPIO1_PC2);
}
void board_led_on(int led)
{
uint16_t reg16;
if (led)
{
/* Turn the LED on */
reg16 = getreg16(SH1_PORTB_DR);
reg16 |= SH1_PBDR_LED;
putreg16(reg16, SH1_PORTB_DR);
}
}
void board_autoled_initialize(void)
{
uint16_t reg16;
/* Setup port B, pin 15 as an output */
reg16 = getreg16(SH1_PFC_PBIOR);
reg16 |= SH1_PBIOR_LED;
putreg16(reg16, SH1_PFC_PBIOR);
/* Setup port B, pin 15 as a normal I/O register */
reg16 = getreg16(SH1_PFC_PBCR1);
reg16 &= ~SH1_PBCR2_LED;
putreg16(reg16, SH1_PFC_PBCR1);
/* Turn the LED off */
reg16 = getreg16(SH1_PORTB_DR);
reg16 &= ~SH1_PBDR_LED;
putreg16(reg16, SH1_PORTB_DR);
}
void board_autoled_off(int led)
{
uint16_t reg16;
if (led)
{
/* Turn the LED off */
reg16 = getreg16(SH1_PORTB_DR);
reg16 &= ~SH1_PBDR_LED;
putreg16(reg16, SH1_PORTB_DR);
}
}
static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords)
{
FAR const uint8_t *ptr = (FAR const uint8_t *)buffer;
uint8_t sr;
/* Loop while thre are bytes remaining to be sent */
spidbg("nwords: %d\n", nwords);
while (nwords > 0)
{
/* While the TX FIFO is not full and there are bytes left to send */
while ((getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_TNF) && nwords)
{
/* Send the data */
putreg16((uint16_t)*ptr, LPC214X_SPI1_DR);
ptr++;
nwords--;
}
}
/* Then discard all card responses until the RX & TX FIFOs are emptied. */
spidbg("discarding\n");
do
{
/* Is there anything in the RX fifo? */
sr = getreg8(LPC214X_SPI1_SR);
if ((sr & LPC214X_SPI1SR_RNE) != 0)
{
/* Yes.. Read and discard */
(void)getreg16(LPC214X_SPI1_DR);
}
/* There is a race condition where TFE may go true just before
* RNE goes true and this loop terminates prematurely. The nasty little
* delay in the following solves that (it could probably be tuned
* to improve performance).
*/
else if ((sr & LPC214X_SPI1SR_TFE) != 0)
{
up_udelay(100);
sr = getreg8(LPC214X_SPI1_SR);
}
}
while ((sr & LPC214X_SPI1SR_RNE) != 0 || (sr & LPC214X_SPI1SR_TFE) == 0);
}
static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
#ifdef CONFIG_DEBUG_SPI
uint32_t regval;
#endif
uint32_t bit = 1 << 20;
/* We do not bother to check if devid == SPIDEV_DISPLAY because that is the
* only thing on the bus.
*/
#ifdef CONFIG_DEBUG_SPI
regval = getreg32(CS_PIN_REGISTER);
#endif
if (selected)
{
/* Enable slave select (low enables) */
putreg32(bit, CS_CLR_REGISTER);
spidbg("CS asserted: %08x->%08x\n", regval, getreg32(CS_PIN_REGISTER));
}
else
{
/* Disable slave select (low enables) */
putreg32(bit, CS_SET_REGISTER);
spidbg("CS de-asserted: %08x->%08x\n", regval, getreg32(CS_PIN_REGISTER));
/* Wait for the TX FIFO not full indication */
while (!(getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_TNF));
putreg16(0xff, LPC214X_SPI1_DR);
/* Wait until TX FIFO and TX shift buffer are empty */
while (getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_BSY);
/* Wait until RX FIFO is not empty */
while (!(getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_RNE));
/* Then read and discard bytes until the RX FIFO is empty */
do
{
(void)getreg16(LPC214X_SPI1_DR);
}
while (getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_RNE);
}
}
/**
* \todo Check for LSE good timeout and return with -1,
* possible ISR optimization? or at least ISR should be cough in case of failure
*/
void stm32_rcc_enablelse(void)
{
/* Enable LSE */
modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON);
/* We could wait for ISR here ... */
while( !(getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) ) up_waste();
/* Select LSE as RTC Clock Source */
modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE);
/* Enable Clock */
modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN);
}
static uavcan::uint64_t sampleUtcFromCriticalSection()
{
# if UAVCAN_STM32_CHIBIOS || UAVCAN_STM32_BAREMETAL
UAVCAN_ASSERT(initialized);
UAVCAN_ASSERT(TIMX->DIER & TIM_DIER_UIE);
volatile uavcan::uint64_t time = time_utc;
volatile uavcan::uint32_t cnt = TIMX->CNT;
if (TIMX->SR & TIM_SR_UIF)
{
cnt = TIMX->CNT;
const uavcan::int32_t add = uavcan::int32_t(USecPerOverflow) +
(utc_accumulated_correction_nsec + utc_correction_nsec_per_overflow) / 1000;
time = uavcan::uint64_t(uavcan::int64_t(time) + add);
}
return time + cnt;
# endif
# if UAVCAN_STM32_NUTTX
UAVCAN_ASSERT(initialized);
UAVCAN_ASSERT(getreg16(TMR_REG(STM32_BTIM_DIER_OFFSET)) & BTIM_DIER_UIE);
volatile uavcan::uint64_t time = time_utc;
volatile uavcan::uint32_t cnt = getreg16(TMR_REG(STM32_BTIM_CNT_OFFSET));
if (getreg16(TMR_REG(STM32_BTIM_SR_OFFSET)) & BTIM_SR_UIF)
{
cnt = getreg16(TMR_REG(STM32_BTIM_CNT_OFFSET));
const uavcan::int32_t add = uavcan::int32_t(USecPerOverflow) +
(utc_accumulated_correction_nsec + utc_correction_nsec_per_overflow) / 1000;
time = uavcan::uint64_t(uavcan::int64_t(time) + add);
}
return time + cnt;
# endif
}
int up_progmem_write(uint32_t addr, const void *buf, size_t count)
{
uint16_t *hword = (uint16_t *)buf;
size_t written = count;
/* STM32 requires half-word access */
if (count & 1)
return -EINVAL;
/* Check for valid address range */
if ( (addr+count) >= STM32_FLASH_SIZE)
return -EFAULT;
/* Get flash ready and begin flashing */
if ( !(getreg32(STM32_RCC_CR) & RCC_CR_HSION) )
return -EPERM;
stm32_flash_unlock();
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG);
for (addr += STM32_FLASH_BASE; count; count--, hword++, addr+=2) {
/* Write half-word and wait to complete */
putreg16(*hword, addr);
while( getreg32(STM32_FLASH_SR) & FLASH_SR_BSY ) up_waste();
/* Verify */
if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRPRT_ERR) {
modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
return -EROFS;
}
if (getreg16(addr) != *hword) {
modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
return -EIO;
}
}
modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
return written;
}
void sercom_slowclk_configure(int gclkgen)
{
static bool configured = false;
uint16_t regval;
/* Since GCLK_SERCOM_SLOW is shard amongst all SERCOM modules, it should
* only be configured one time.
*/
if (!configured)
{
/* Set up the SERCOM_GCLK_ID_SLOW clock */
regval = (SERCOM_GCLK_ID_SLOW << GCLK_CLKCTRL_ID_SHIFT);
/* Select and disable the SERCOM_GCLK_ID_SLOW generic clock */
putreg16(regval, SAM_GCLK_CLKCTRL);
/* Wait for clock to become disabled */
while ((getreg16(SAM_GCLK_CLKCTRL) & GCLK_CLKCTRL_CLKEN) != 0);
/* Select the SERCOM_GCLK_ID_SLOW clock source generator */
regval |= (uint16_t)gclkgen << GCLK_CLKCTRL_GEN_SHIFT;
/* Write the new configuration */
putreg16(regval, SAM_GCLK_CLKCTRL);
/* Enable the GCLK_SERCOM_SLOW generic clock and lock further
* writes to this GCLK. When this bit is written, it will lock
* further writes to the generic clock pointed by the CLKCTRL.ID. The
* generic clock generator pointed by CLKCTRL.GEN and the GENDIV.DIV
* will also be locked.
*
* We lock the SERCOM slow clock because it is common to all SERCOM modules
* and, once set, should not be changed again.
*/
regval |= (/* GCLK_CLKCTRL_WRTLOCK | */ GCLK_CLKCTRL_CLKEN);
putreg16(regval, SAM_GCLK_CLKCTRL);
/* Now we are configured */
configured = true;
}
}
void board_autoled_initialize(void)
{
uint16_t reg16;
/* Set normal function output */
reg16 = getreg16(STR71X_GPIO1_PC0);
reg16 |= STR71X_LEDGPIO1_BITS;
putreg16(reg16, STR71X_GPIO1_PC0);
reg16 = getreg16(STR71X_GPIO1_PC1);
reg16 &= ~STR71X_LEDGPIO1_BITS;
putreg16(reg16, STR71X_GPIO1_PC1);
reg16 = getreg16(STR71X_GPIO1_PC2);
reg16 |= STR71X_LEDGPIO1_BITS;
putreg16(reg16, STR71X_GPIO1_PC2);
/* Clear the LEDs (1 clears; 0 sets) */
reg16 = getreg16(STR71X_GPIO1_PD);
reg16 |= STR71X_LEDGPIO1_BITS;
putreg16(reg16, STR71X_GPIO1_PD);
}
static void stm32_ili93414ws_spirecvmode(void)
{
/* Set to bidirectional rxonly mode */
stm32_ili93414ws_modifycr1(0, SPI_CR1_BIDIOE);
/* Disable spi */
stm32_ili93414ws_spidisable();
/* Clear the rx buffer if received data exist e.g. from previous
* broken transfer.
*/
(void)getreg16(ILI93414WS_SPI_DR);
}
