void up_enable_irq(int irq)
{
/* System exceptions cannot be disabled */
if (irq >= Z16F_IRQ_IRQ0)
{
/* Enable the interrupt by setting the corresponding bit in the
* appropriate IRQ enable register. The enable low
* register is assumed to be zero, resulting in "nomimal" interrupt
* priority.
*/
if (irq < Z16F_IRQ_IRQ1)
{
putreg8((getreg8(Z16F_IRQ0_ENH) | Z16F_IRQ0_BIT(irq)), Z16F_IRQ0_ENH);
}
else if (irq < Z16F_IRQ_IRQ2)
{
putreg8((getreg8(Z16F_IRQ1_ENH) | Z16F_IRQ1_BIT(irq)), Z16F_IRQ1_ENH);
}
else if (irq < NR_IRQS)
{
putreg8((getreg8(Z16F_IRQ2_ENH) | Z16F_IRQ2_BIT(irq)), Z16F_IRQ2_ENH);
}
}
}
void up_maskack_irq(int irq)
{
/* System exceptions cannot be disabled or acknowledged */
if (irq >= Z16F_IRQ_IRQ0)
{
/* Disable the interrupt by clearing the corresponding bit in the
* appropriate IRQ enable register and acknowledge it by setting the
* corresponding bit in the IRQ status register.
*/
if (irq < Z16F_IRQ_IRQ1)
{
putreg8((getreg8(Z16F_IRQ0_ENH) & ~Z16F_IRQ0_BIT(irq)), Z16F_IRQ0_ENH);
putreg8(Z16F_IRQ0_BIT(irq), Z16F_IRQ0);
}
else if (irq < Z16F_IRQ_IRQ2)
{
putreg8((getreg8(Z16F_IRQ1_ENH) & ~Z16F_IRQ1_BIT(irq)), Z16F_IRQ1_ENH);
putreg8(Z16F_IRQ1_BIT(irq), Z16F_IRQ2);
}
else if (irq < NR_IRQS)
{
putreg8((getreg8(Z16F_IRQ2_ENH) & ~Z16F_IRQ2_BIT(irq)), Z16F_IRQ2_ENH);
putreg8(Z16F_IRQ2_BIT(irq), Z16F_IRQ2);
}
}
}
void calypso_fiq(void)
{
uint8_t num, tmp;
uint32_t *regs;
/* XXX: What is this???
* Passed to but ignored in IRQ handlers
* Only valid meaning is apparently non-NULL == IRQ context */
regs = (uint32_t *)current_regs;
current_regs = (uint32_t *)#
/* Detect & deliver like an IRQ but we are in FIQ context */
num = getreg8(IRQ_REG(FIQ_NUM)) & 0x1f;
irq_dispatch(num, regs);
/* Start new FIQ agreement */
tmp = getreg8(IRQ_REG(IRQ_CTRL));
tmp |= 0x02;
putreg8(tmp, IRQ_REG(IRQ_CTRL));
current_regs = regs;
}
void up_disable_irq(int irq)
{
/* System exceptions cannot be disabled */
if (irq >= Z16F_IRQ_IRQ0)
{
/* Disable the interrupt by clearing the corresponding bit in the
* appropriate IRQ enable high register. The enable low
* register is assumed to be zero, resulting interrupt disabled.
*/
if (irq < Z16F_IRQ_IRQ1)
{
putreg8((getreg8(Z16F_IRQ0_ENH) & ~Z16F_IRQ0_BIT(irq)), Z16F_IRQ0_ENH);
}
else if (irq < Z16F_IRQ_IRQ2)
{
putreg8((getreg8(Z16F_IRQ1_ENH) & ~Z16F_IRQ1_BIT(irq)), Z16F_IRQ1_ENH);
}
else if (irq < NR_IRQS)
{
putreg8((getreg8(Z16F_IRQ2_ENH) & ~Z16F_IRQ2_BIT(irq)), Z16F_IRQ2_ENH);
}
}
}
static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords)
{
FAR uint8_t *ptr = (FAR uint8_t*)buffer;
uint32_t rxpending = 0;
/* While there is remaining to be sent (and no synchronization error has occurred) */
spidbg("nwords: %d\n", nwords);
while (nwords || rxpending)
{
/* Fill the transmit FIFO with 0xff...
* Write 0xff to the data register while (1) the TX FIFO is
* not full, (2) we have not exceeded the depth of the TX FIFO,
* and (3) there are more bytes to be sent.
*/
spivdbg("TX: rxpending: %d nwords: %d\n", rxpending, nwords);
while ((getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_TNF) &&
(rxpending < LPC214X_SPI1_FIFOSZ) && nwords)
{
putreg16(0xff, LPC214X_SPI1_DR);
nwords--;
rxpending++;
}
/* Now, read the RX data from the RX FIFO while the RX FIFO is not empty */
spivdbg("RX: rxpending: %d\n", rxpending);
while (getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_RNE)
{
*ptr++ = (uint8_t)getreg16(LPC214X_SPI1_DR);
rxpending--;
}
}
}
void up_decodeirq(uint32_t *regs)
{
uint8_t num, tmp;
uint32_t *saved_regs;
/* XXX: What is this???
* Passed to but ignored in IRQ handlers
* Only valid meaning is apparently non-NULL == IRQ context */
saved_regs = (uint32_t *)current_regs;
current_regs = regs;
/* Detect & deliver the IRQ */
num = getreg8(IRQ_REG(IRQ_NUM)) & 0x1f;
irq_dispatch(num, regs);
/* Start new IRQ agreement */
tmp = getreg8(IRQ_REG(IRQ_CTRL));
tmp |= 0x01;
putreg8(tmp, IRQ_REG(IRQ_CTRL));
current_regs = saved_regs;
}
static int z16f_receive(struct uart_dev_s *dev, uint32_t *status)
{
struct z16f_uart_s *priv = (struct z16f_uart_s*)dev->priv;
uint8_t rxd;
uint8_t stat0;
rxd = getreg8(priv->uartbase + Z16F_UART_RXD);
stat0 = getreg8(priv->uartbase + Z16F_UART_STAT0);
*status = (uint32_t)rxd | (((uint32_t)stat0) << 8);
return rxd;
}
static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
#ifdef CONFIG_DEBUG_SPI
uint32_t regval;
#endif
uint32_t bit = 1 << 20;
/* We do not bother to check if devid == SPIDEV_DISPLAY because that is the
* only thing on the bus.
*/
#ifdef CONFIG_DEBUG_SPI
regval = getreg32(CS_PIN_REGISTER);
#endif
if (selected)
{
/* Enable slave select (low enables) */
putreg32(bit, CS_CLR_REGISTER);
spidbg("CS asserted: %08x->%08x\n", regval, getreg32(CS_PIN_REGISTER));
}
else
{
/* Disable slave select (low enables) */
putreg32(bit, CS_SET_REGISTER);
spidbg("CS de-asserted: %08x->%08x\n", regval, getreg32(CS_PIN_REGISTER));
/* Wait for the TX FIFO not full indication */
while (!(getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_TNF));
putreg16(0xff, LPC214X_SPI1_DR);
/* Wait until TX FIFO and TX shift buffer are empty */
while (getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_BSY);
/* Wait until RX FIFO is not empty */
while (!(getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_RNE));
/* Then read and discard bytes until the RX FIFO is empty */
do
{
(void)getreg16(LPC214X_SPI1_DR);
}
while (getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_RNE);
}
}
static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords)
{
FAR const uint8_t *ptr = (FAR const uint8_t *)buffer;
uint8_t sr;
/* Loop while thre are bytes remaining to be sent */
spidbg("nwords: %d\n", nwords);
while (nwords > 0)
{
/* While the TX FIFO is not full and there are bytes left to send */
while ((getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_TNF) && nwords)
{
/* Send the data */
putreg16((uint16_t)*ptr, LPC214X_SPI1_DR);
ptr++;
nwords--;
}
}
/* Then discard all card responses until the RX & TX FIFOs are emptied. */
spidbg("discarding\n");
do
{
/* Is there anything in the RX fifo? */
sr = getreg8(LPC214X_SPI1_SR);
if ((sr & LPC214X_SPI1SR_RNE) != 0)
{
/* Yes.. Read and discard */
(void)getreg16(LPC214X_SPI1_DR);
}
/* There is a race condition where TFE may go true just before
* RNE goes true and this loop terminates prematurely. The nasty little
* delay in the following solves that (it could probably be tuned
* to improve performance).
*/
else if ((sr & LPC214X_SPI1SR_TFE) != 0)
{
up_udelay(100);
sr = getreg8(LPC214X_SPI1_SR);
}
}
while ((sr & LPC214X_SPI1SR_RNE) != 0 || (sr & LPC214X_SPI1SR_TFE) == 0);
}
static void m16c_setleds(uint8_t gybits, uint8_t rbit)
{
uint8_t regval;
regval = getreg8(GREENYELLOW_LED_PORT);
regval &= ~GREENYELLOW_LED_MASK;
regval |= gybits;
putreg8(regval, GREENYELLOW_LED_PORT);
regval = getreg8(RED_LED_PORT);
regval &= ~RED_LED_MASK;
regval |= rbit;
putreg8(regval, RED_LED_PORT);
}
void up_earlyserialinit(void)
{
uint8_t regval;
/* Configure UART alternate pin functions. This may duplicate logic in
* z16f_lowuartinit() or z16f_lowinit().
*/
#ifdef CONFIG_Z16F_UART0
/* UART0 is PA4 and PA5, alternate function 1 */
regval = getreg8(Z16F_GPIOA_AFL);
regval |= 0x30;
putreg8(regval, Z16F_GPIOA_AFL);
regval = getreg8(Z16F_GPIOA_AFH);
regval &= ~0x30;
putreg8(regval, Z16F_GPIOA_AFH);
#endif
#ifdef CONFIG_Z16F_UART1
/* UART1 is PD4 and PD5, alternate function 1 */
regval = getreg8(Z16F_GPIOD_AFL);
regval |= 0x30;
putreg8(regval, Z16F_GPIOD_AFL);
regval = getreg8(Z16F_GPIOD_AFH);
regval &= ~0x30;
putreg8(regval, Z16F_GPIOD_AFH);
#endif
/* Disable UART interrupts */
#ifdef TTYS0_DEV
(void)z16f_disableuartirq(&TTYS0_DEV);
#endif
#ifdef TTYS1_DEV
(void)z16f_disableuartirq(&TTYS1_DEV);
#endif
/* Configuration any serial console */
#ifdef CONSOLE_DEV
CONSOLE_DEV.isconsole = true;
z16f_setup(&CONSOLE_DEV);
#endif
}
static int hcs12_interrupt(uint16_t base, int irq0, uint8_t valid, void *context)
{
uint8_t pending;
uint8_t bit;
int irq;
/* Get the set of enabled (unmasked) interrupts pending on this port */
pending = getreg8(base+HCS12_PIM_IF_OFFSET) && getreg8(base+HCS12_PIM_IE_OFFSET);
/* Then check each bit in the set of interrupts */
for (bit = 1, irq = irq0; pending != 0; bit <<= 1)
{
/* We may need to skip over some bits in the interrupt register (without
* incrementing the irq value.
*/
if ((valid & bit) != 0)
{
/* This is a real interrupt bit -- Check if an unmasked interrupt
* is pending.
*/
if ((pending & bit) != 0)
{
/* Yes.. clear the pending interrupt by writing '1' to the
* flags registers.
*/
putreg8(bit, base+HCS12_PIM_IF_OFFSET);
/* Re-deliver the IRQ (recurses! We got here from irq_dispatch!) */
irq_dispatch(irq, context);
/* Remove this from the set of pending interrupts */
pending &= ~bit;
}
/* Bump up the IRQ number for the next pass through the loop */
irq++;
}
}
return OK;
}
static int z16f_txinterrupt(int irq, void *context)
{
struct uart_dev_s *dev = NULL;
struct z16f_uart_s *priv;
uint8_t status;
if (g_uart1priv.txirq == irq)
{
dev = &g_uart1port;
}
else if (g_uart0priv.txirq == irq)
{
dev = &g_uart0port;
}
else
{
PANIC();
}
priv = (struct z16f_uart_s*)dev->priv;
/* Verify that the transmit data register is empty */
status = getreg8(priv->uartbase + Z16F_UART_STAT0);
if (status & Z16F_UARTSTAT0_TDRE)
{
/* Handle outgoing, transmit bytes */
uart_xmitchars(dev);
}
return OK;
}
ssize_t up_progmem_ispageerased(size_t page)
{
size_t addr;
size_t count;
size_t bwritten = 0;
if (page >= (EFM32_FLASH_NPAGES+EFM32_USERDATA_NPAGES))
{
return -EFAULT;
}
/* Verify */
for (addr = up_progmem_getaddress(page), count = up_progmem_pagesize(page);
count; count--, addr++)
{
if (getreg8(addr) != 0xff)
{
bwritten++;
}
}
return bwritten;
}
void up_lowputc(char ch)
{
#if defined HAVE_UART_DEVICE && defined HAVE_SERIAL_CONSOLE
#ifdef CONFIG_KINETIS_UARTFIFOS
/* Wait until there is space in the TX FIFO: Read the number of bytes
* currently in the FIFO and compare that to the size of the FIFO. If
* there are fewer bytes in the FIFO than the size of the FIFO, then we
* are able to transmit.
*/
# error "Missing logic"
#else
/* Wait until the transmit data register is "empty" (TDRE). This state
* depends on the TX watermark setting and may not mean that the transmit
* buffer is truly empty. It just means that we can now add another
* characterto the transmit buffer without exceeding the watermark.
*
* NOTE: UART0 has an 8-byte deep FIFO; the other UARTs have no FIFOs
* (1-deep). There appears to be no way to know when the FIFO is not
* full (other than reading the FIFO length and comparing the FIFO count).
* Hence, the FIFOs are not used in this implementation and, as a result
* TDRE indeed mean that the single output buffer is available.
*
* Performance on UART0 could be improved by enabling the FIFO and by
* redesigning all of the FIFO status logic.
*/
while ((getreg8(CONSOLE_BASE+KINETIS_UART_S1_OFFSET) & UART_S1_TDRE) == 0);
#endif
/* Then write the character to the UART data register */
putreg8((uint8_t)ch, CONSOLE_BASE+KINETIS_UART_D_OFFSET);
#endif
}
void str71x_disable_xtiirq(int irq)
{
uint8_t regval;
int bit;
int ndx;
/* Disable the external interrupt */
if (irq >= STR71X_IRQ_FIRSTXTI && irq <= NR_IRQS)
{
/* Decide if we use the lower or upper regiser */
bit = irq - STR71X_IRQ_FIRSTXTI;
ndx = 0;
if (bit > 7)
{
/* Select the high register */
bit -= 8;
ndx = 1;
}
/* Disable the interrupt be clearing the corresponding mask bit
* the XTI_MRL/H register.
*/
regval = getreg8(g_xtiregs[ndx].mr);
regval &= ~(1 << bit);
putreg8(regval, g_xtiregs[ndx].mr);
}
}
static void z16f_sysclkinit(int clockid, uint32_t frequency)
{
int count;
/* In this configuration, we support only the external oscillator/clock
* the the source of the system clock (__DEFCLK is ignored).
*/
if ((getreg8(Z16F_OSC_CTL) & 0x03) != 1)
{
/* No divider for the oscillator */
putreg8(0x00, Z16F_OSC_DIV);
/* Enable external oscillator */
putreg8(0xe7, Z16F_OSC_CTL); /* Unlock the crystal oscillator */
putreg8(0x18, Z16F_OSC_CTL);
putreg8(0xe0, Z16F_OSC_CTL); /* INTEN+XTLEN+WDTEN */
/* Wait for oscillator to stabilize */
for (count = 0; count < 10000; count++);
/* Select external oscillator (SCLKSEL=1) */
putreg8(0xe7, Z16F_OSC_CTL); /* Unlock the crystal oscillator */
putreg8(0x18, Z16F_OSC_CTL);
putreg8(0xe0 | 1, Z16F_OSC_CTL); /* Use the external osc/clock as system clock */
}
}
void up_buttoninit(void)
{
uint8_t regval;
regval = getreg8(M16C_PD8);
regval |= (SW1_BIT | SW2_BIT | SW3_BIT);
putreg8(regval, M16C_PD8);
}
static inline void up_clren(void)
{
/* Clear bit 1 of port 6 */
register uint8_t regval = getreg8(M16C_P6);
regval &= ~(1 << 1);
putreg8(regval, M16C_P6);
}
static inline void up_seten(void)
{
/* Set bit 1 of port 6 */
register uint8_t regval = getreg8(M16C_P6);
regval |= (1 << 1);
putreg8(regval, M16C_P6);
}
uint16_t hwtimer_read(int num)
{
uint8_t ctl = getreg8(TIMER_REG(num, CNTL_TIMER));
/* somehow a read results in an abort */
if ((ctl & (CNTL_START|CNTL_CLOCK_ENABLE)) != (CNTL_START|CNTL_CLOCK_ENABLE))
return 0xFFFF;
return getreg16(TIMER_REG(num, READ_TIMER));
}
void kinetis_uartreset(uintptr_t uart_base)
{
uint8_t regval;
/* Just disable the transmitter and receiver */
regval = getreg8(uart_base+KINETIS_UART_C2_OFFSET);
regval &= ~(UART_C2_RE | UART_C2_TE);
putreg8(regval, uart_base+KINETIS_UART_C2_OFFSET);
}
static int str71x_xtiinterrupt(int irq, FAR void *context)
{
uint16_t enabled = (uint16_t)getreg8(STR71X_XTI_MRH) << 8 |
(uint16_t)getreg8(STR71X_XTI_MRL);
uint16_t pending = (uint16_t)getreg8(STR71X_XTI_PRH) << 8 |
(uint16_t)getreg8(STR71X_XTI_PRL);
uint16_t mask;
/* Dispatch the interrupts, the actions performed by the interrupt
* handlers should clear the interrupt at the external source of the
* interrupt. We need to clear the interrupts at the source before
* clearing the pending interrupts (see below).
*/
pending &= enabled;
for (irq = STR71X_IRQ_FIRSTXTI, mask = 0x0001;
irq < NR_IRQS && pending != 0;
irq++, mask <<= 1)
{
/* Is this interrupt pending? */
if ((pending & mask) != 0)
{
/* Deliver the IRQ */
irq_dispatch(irq, context);
pending &= ~mask;
}
}
/* Clear the pending interrupts. This should be safe: "it is necessary to
* clear at least one pending bit: this operation allows a rising edge to be
* generated on the internal line (if there is at least one more pending bit
* set and not masked) and so to set the interrupt controller pending bit
* again.
*/
putreg8(0, STR71X_XTI_PRH);
putreg8(0, STR71X_XTI_PRL);
return OK;
}
bool lpc43_gpio_read(uint16_t gpiocfg)
{
unsigned int port = ((gpiocfg & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
unsigned int pin = ((gpiocfg & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
DEBUGASSERT(port < NUM_GPIO_PORTS && pin < NUM_GPIO_PINS);
/* Get the value of the pin from the pin byte register */
return (getreg8(LPC43_GPIO_B(port, pin)) & GPIO_B) != 0;
}
void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits)
{
irqstate_t flags;
uint8_t regval;
flags = enter_critical_section();
regval = getreg8(addr);
regval &= ~clearbits;
regval |= setbits;
putreg8(regval, addr);
leave_critical_section(flags);
}
void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits)
{
irqstate_t flags;
uint8_t regval;
flags = irqsave();
regval = getreg8(addr);
regval &= ~clearbits;
regval |= setbits;
putreg8(regval, addr);
irqrestore(flags);
}
const char *stm32_getchipid(void)
{
static char cpuid[12];
int i;
for (i = 0; i < 12; i++)
{
cpuid[i] = getreg8(0x1ffff7e8+i);
}
return cpuid;
}
void z8_uartconfigure(void)
{
uint16_t brg;
uint8_t val;
/* Configure GPIO Port A pins 4 & 5 for alternate function */
putreg8(0x02, PAADDR);
val = getreg8(PACTL) | 0x30; /* Set bits in alternate function register */
putreg8(val, PACTL);
putreg8(0x07, PAADDR);
val = getreg8(PACTL) & 0xcf; /* Reset bits in alternate function set-1 register */
putreg8(val, PACTL);
putreg8(0x08, PAADDR);
val = getreg8(PACTL) & 0xcf; /* Reset bits in alternate function set-2 register */
putreg8(val, PACTL);
putreg8(0x00, PAADDR);
#ifdef EZ8_UART1
/* Configure GPIO Port D pins 4 & 5 for alternate function */
putreg8(0x02, PAADDR);
val = getreg8(PDCTL) | 0x30; /* Set bits in alternate function register */
putreg8(val, PDCTL);
putreg8(0x07, PDADDR);
val = getreg8(PDCTL) & 0xcf; /* Reset bits in alternate function set-1 register */
putreg8(val, PDCTL);
putreg8(0x08, PDADDR);
val = getreg8(PDCTL) & 0xcf; /* Reset bits in alternate function set-2 register */
putreg8(val, PDCTL);
putreg8(0x00, PDADDR);
#endif
}
void up_lcdinit(void)
{
uint8_t regval;
/* Enable writing to PD9 by selecting bit 2 in the protection register */
regval = getreg8(M16C_PRCR);
regval |= (1 << 2);
putreg8(regval, M16C_PRCR);
/* We can't read PD9, so we can't OR the values in */
putreg8(0x0f, M16C_PD9);
/* Set EN (port 6 bit 1) and Set RS (port 6 bit 0) as outputs */
regval = getreg8(M16C_P6);
regval |= (1 << 1) | (1 << 0);
putreg8(regval, M16C_P6);
regval = getreg8(M16C_PD6);
regval |= (1 << 1) | (1 << 0);
putreg8(regval, M16C_PD6);
/* Set EN low */
up_clren();
/* Write the reset sequence */
up_lcdwrite(false, 0x33);
up_lcddelay(20);
up_lcdwrite(false, 0x32);
up_lcddelay(20);
up_lcdwrite(false, FUNCTION_SET); /* reset sequence */
up_lcdwrite(false, FUNCTION_SET);
up_lcdwrite(false, LCD_CURSOR_OFF);
up_lcdwrite(false, LCD_CLEAR);
up_lcdwrite(false, LCD_HOME_L1);
}
static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
uint32_t bit = 1 << 20;
if (selected)
{
/* Enable slave select (low enables) */
spidbg("CD asserted\n");
putreg32(bit, CS_CLR_REGISTER);
}
else
{
/* Disable slave select (low enables) */
spidbg("CD de-asserted\n");
putreg32(bit, CS_SET_REGISTER);
/* Wait for the TX FIFO not full indication */
while (!(getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_TNF));
putreg16(0xff, LPC214X_SPI1_DR);
/* Wait until TX FIFO and TX shift buffer are empty */
while (getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_BSY);
/* Wait until RX FIFO is not empty */
while (!(getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_RNE));
/* Then read and discard bytes until the RX FIFO is empty */
do
{
(void)getreg16(LPC214X_SPI1_DR);
}
while (getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_RNE);
}
}
