void do_irq() { unsigned int irq = gic_acknowledge_irq(); if (irq == SPURIOUS_IRQ) return; if (table[irq]) table[irq](); gic_complete_irq(irq); }
static void gic_cpu_write(void *opaque, target_phys_addr_t offset, uint32_t value) { gic_state *s = (gic_state *)opaque; offset -= s->base; switch (offset) { case 0x00: /* Control */ s->cpu_enabled = (value & 1); DPRINTF("CPU %sabled\n", s->cpu_enabled ? "En" : "Dis"); break; case 0x04: /* Priority mask */ s->priority_mask = (value & 0x3ff); break; case 0x08: /* Binary Point */ /* ??? Not implemented. */ break; case 0x10: /* End Of Interrupt */ return gic_complete_irq(s, value & 0x3ff); default: cpu_abort (cpu_single_env, "gic_cpu_writeb: Bad offset %x\n", offset); return; } gic_update(s); }