void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority)
{
gic_set_irq_priority(irq_id, priority);
gic_set_irq_security(irq_id, false); // set IRQ as non-secure
gic_set_cpu_target(irq_id, cpu_id, true);
gic_enable_irq(irq_id, true);
}
void CAN_Ctrl::init(uint32_t baudrate){
if(!initialized){
initialized=true;
can_init(can, CAN_LAST_MB);
imx_flexcan canmodule;
can_set_can_attributes(&canmodule,mapToFlexcanBitrate(baudrate),can);
can_update_bitrate(&canmodule);
for(int i=0;i<CAN_NUMBER_OF_BUFFERS;i++){
can_mb_int_ack(can,i);
}
//configure fifo
HW_FLEXCAN_MCR_SET(can->instance,BM_FLEXCAN_MCR_FEN); //set RFEN
HW_FLEXCAN_MCR_SET(can->instance,BM_FLEXCAN_MCR_BCC);//set IRMQ
HW_FLEXCAN_MCR_CLR(can->instance,BM_FLEXCAN_MCR_IDAM); // filter format A
REG_SET(REG_RXFGMASK(can->base),~0);
//conif RFFN
REG_SET(REG_CTRL2(can->base),0xF <<REG_CTRL2_RFFN_SHIFT);
//configure other flags
HW_FLEXCAN_MCR_SET(can->instance,BM_FLEXCAN_MCR_SRX_DIS); //No self recv
REG_SET(REG_CTRL2(can->base),REG_CTRL2_RRS_MASK);
//configure irq
irq_hdlr_t handler;
uint32_t irqid;
if(this==&CANs[0]){
irqid=IMX_INT_FLEXCAN1;
handler=&CAN1_IRQHandler;
}else if(this==&CANs[1]){
irqid=IMX_INT_FLEXCAN2;
handler=&CAN2_IRQHandler;
}
register_interrupt_routine(irqid,handler);
enable_interrupt(irqid,cpu_get_current(),128);
gic_set_irq_security(irqid,false);
setupFilters();
can_exit_freeze(can);
can_enable_mb_interrupt(can,FIFO_FLAG_DATARDY);
}
}
