static void gpio_rcar_irq_enable(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct gpio_rcar_priv *p = gpiochip_get_data(gc); gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d))); }
static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p, unsigned int hwirq, bool active_high_rising_edge, bool level_trigger, bool both) { unsigned long flags; /* follow steps in the GPIO documentation for * "Setting Edge-Sensitive Interrupt Input Mode" and * "Setting Level-Sensitive Interrupt Input Mode" */ spin_lock_irqsave(&p->lock, flags); /* Configure postive or negative logic in POSNEG */ gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge); /* Configure edge or level trigger in EDGLEVEL */ gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger); /* Select one edge or both edges in BOTHEDGE */ if (p->has_both_edge_trigger) gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both); /* Select "Interrupt Input Mode" in IOINTSEL */ gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true); /* Write INTCLR in case of edge trigger */ if (!level_trigger) gpio_rcar_write(p, INTCLR, BIT(hwirq)); spin_unlock_irqrestore(&p->lock, flags); }
static void gpio_rcar_irq_enable(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv, gpio_chip); gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d))); }
static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs, int bit, bool value) { u32 tmp = gpio_rcar_read(p, offs); if (value) tmp |= BIT(bit); else tmp &= ~BIT(bit); gpio_rcar_write(p, offs, tmp); }
static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id) { struct gpio_rcar_priv *p = dev_id; u32 pending; unsigned int offset, irqs_handled = 0; while ((pending = gpio_rcar_read(p, INTDT))) { offset = __ffs(pending); gpio_rcar_write(p, INTCLR, BIT(offset)); generic_handle_irq(irq_find_mapping(p->irq_domain, offset)); irqs_handled++; } return irqs_handled ? IRQ_HANDLED : IRQ_NONE; }
static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask, unsigned long *bits) { struct gpio_rcar_priv *p = gpiochip_get_data(chip); unsigned long flags; u32 val, bankmask; bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0); if (chip->valid_mask) bankmask &= chip->valid_mask[0]; if (!bankmask) return; spin_lock_irqsave(&p->lock, flags); val = gpio_rcar_read(p, OUTDT); val &= ~bankmask; val |= (bankmask & bits[0]); gpio_rcar_write(p, OUTDT, val); spin_unlock_irqrestore(&p->lock, flags); }
static void gpio_rcar_irq_disable(struct irq_data *d) { struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d); gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d))); }