void gps_end(void){ usart_disable(GPS_USART); gpio_write_bit(GPIOA, 8, 0); }
int board_early_init_f(void) { u32 sdr0_pfc1, sdr0_pfc2; u32 reg; /* PLB Write pipelining disabled. Denali Core workaround */ mtdcr(PLB0_ACR, 0xDE000000); mtdcr(PLB1_ACR, 0xDE000000); /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */ mtdcr(UIC0ER, 0x00000000); /* disable all */ mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */ mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */ mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ mtdcr(UIC0SR, 0xffffffff); /* clear all */ mtdcr(UIC1SR, 0xffffffff); /* clear all */ mtdcr(UIC1ER, 0x00000000); /* disable all */ mtdcr(UIC1CR, 0x00000000); /* all non-critical */ mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */ mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ mtdcr(UIC1SR, 0xffffffff); /* clear all */ mtdcr(UIC2SR, 0xffffffff); /* clear all */ mtdcr(UIC2ER, 0x00000000); /* disable all */ mtdcr(UIC2CR, 0x00000000); /* all non-critical */ mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */ mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ mtdcr(UIC2SR, 0xffffffff); /* clear all */ /* Trace Pins are disabled. SDR0_PFC0 Register */ mtsdr(SDR0_PFC0, 0x0); /* select Ethernet pins */ mfsdr(SDR0_PFC1, sdr0_pfc1); /* SMII via ZMII */ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_6; mfsdr(SDR0_PFC2, sdr0_pfc2); sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_6; /* enable SPI (SCP) */ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL; mtsdr(SDR0_PFC2, sdr0_pfc2); mtsdr(SDR0_PFC1, sdr0_pfc1); mtsdr(SDR0_PFC4, 0x80000000); /* PCI arbiter disabled */ /* PCI Host Configuration disbaled */ mfsdr(SDR0_PCI0, reg); reg = 0; mtsdr(SDR0_PCI0, 0x00000000 | reg); gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1); #if CONFIG_POST & CONFIG_SYS_POST_BSPEC1 gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 1); reg = 0; /* reuse as counter */ out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) & ~CONFIG_SYS_DSPIC_TEST_MASK); while (!gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) { udelay(1000); } gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 0); if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) { /* set "boot error" flag */ out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) | CONFIG_SYS_DSPIC_TEST_MASK); } #endif /* * Reset PHY's: * The PHY's need a 2nd reset pulse, since the MDIO address is latched * upon reset, and with the first reset upon powerup, the addresses are * not latched reliable, since the IRQ line is multiplexed with an * MDIO address. A 2nd reset at this time will make sure, that the * correct address is latched. */ gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1); gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1); udelay(1000); gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0); gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0); udelay(1000); gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1); gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1); return 0; }
void disableUSB (void) { // These are just guesses about how to do this // TODO: real disable function usbDsbISR(); gpio_write_bit(USB_DISC_BANK,USB_DISC_PIN,1); }
void board_reset(void) { gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1); }
void i2c_master_release_bus(const i2c_dev *dev) { gpio_write_bit(dev->gpio_port, dev->scl_pin, 1); gpio_write_bit(dev->gpio_port, dev->sda_pin, 1); gpio_set_mode(dev->gpio_port, dev->scl_pin, GPIO_OUTPUT_OD); gpio_set_mode(dev->gpio_port, dev->sda_pin, GPIO_OUTPUT_OD); }
void gd405ex_setup_hw(void) { gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED_N, 0); gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED, 1); }
void set_gpio(int pin, int value) { gpio_set_dir_out(pin); gpio_write_bit(pin, value); }