int gpu_set_target_clk_vol_pending(int clk)
{
int ret = 0, target_clk = 0, target_vol = 0;
int prev_clk = 0;
struct kbase_device *kbdev = pkbdev;
struct exynos_context *platform = (struct exynos_context *) kbdev->platform_context;
DVFS_ASSERT(platform);
target_clk = gpu_check_target_clock(platform, clk);
if (target_clk < 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u,
"%s: mismatch clock error (source %d, target %d)\n", __func__, clk, target_clk);
return -1;
}
target_vol = MAX(gpu_dvfs_get_voltage(target_clk) + platform->voltage_margin, platform->cold_min_vol);
prev_clk = gpu_get_cur_clock(platform);
GPU_SET_CLK_VOL(kbdev, platform->cur_clock, target_clk, target_vol);
GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "pending clk[%d -> %d], vol[%d (margin : %d)]\n",
prev_clk, gpu_get_cur_clock(platform), gpu_get_cur_voltage(platform), platform->voltage_margin);
ret = gpu_update_cur_level(platform);
return ret;
}
int gpu_set_target_clk_vol(int clk, bool pending_is_allowed)
{
int ret = 0, target_clk = 0, target_vol = 0;
int prev_clk = 0;
struct kbase_device *kbdev = pkbdev;
struct exynos_context *platform = (struct exynos_context *) kbdev->platform_context;
DVFS_ASSERT(platform);
if (!gpu_control_is_power_on(pkbdev)) {
GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "%s: can't set clock and voltage in the power-off state!\n", __func__);
return -1;
}
mutex_lock(&platform->gpu_clock_lock);
#ifdef CONFIG_MALI_DVFS
if (pending_is_allowed && platform->dvs_is_enabled) {
if (!platform->dvfs_pending && clk < platform->cur_clock) {
platform->dvfs_pending = clk;
GPU_LOG(DVFS_DEBUG, DUMMY, 0u, 0u, "pending to change the clock [%d -> %d\n", platform->cur_clock, platform->dvfs_pending);
} else if (clk > platform->cur_clock) {
platform->dvfs_pending = 0;
}
mutex_unlock(&platform->gpu_clock_lock);
return 0;
} else {
platform->dvfs_pending = 0;
}
#endif /* CONFIG_MALI_DVFS */
target_clk = gpu_check_target_clock(platform, clk);
if (target_clk < 0) {
mutex_unlock(&platform->gpu_clock_lock);
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u,
"%s: mismatch clock error (source %d, target %d)\n", __func__, clk, target_clk);
return -1;
}
target_vol = MAX(gpu_dvfs_get_voltage(target_clk) + platform->voltage_margin, platform->cold_min_vol);
prev_clk = gpu_get_cur_clock(platform);
GPU_SET_CLK_VOL(kbdev, prev_clk, target_clk, target_vol);
ret = gpu_update_cur_level(platform);
mutex_unlock(&platform->gpu_clock_lock);
GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "clk[%d -> %d], vol[%d (margin : %d)]\n",
prev_clk, gpu_get_cur_clock(platform), gpu_get_cur_voltage(platform), platform->voltage_margin);
return ret;
}
int gpu_set_target_clk_vol_pending(int clk)
{
int ret = 0, target_clk = 0, target_vol = 0;
int prev_clk = 0;
struct kbase_device *kbdev = pkbdev;
struct exynos_context *platform = (struct exynos_context *) kbdev->platform_context;
#ifdef CONFIG_EXYNOS_CL_DVFS_G3D
int level = 0;
#endif
DVFS_ASSERT(platform);
target_clk = gpu_check_target_clock(platform, clk);
if (target_clk < 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u,
"%s: mismatch clock error (source %d, target %d)\n", __func__, clk, target_clk);
return -1;
}
target_vol = MAX(gpu_dvfs_get_voltage(target_clk) + platform->voltage_margin, platform->cold_min_vol);
target_vol = target_vol < (int) platform->table[0].voltage ? target_vol : (int) platform->table[0].voltage;
prev_clk = gpu_get_cur_clock(platform);
#ifdef CONFIG_EXYNOS_CL_DVFS_G3D
level = gpu_dvfs_get_level(clk);
exynos7420_cl_dvfs_stop(ID_G3D, level);
#endif
GPU_SET_CLK_VOL(kbdev, platform->cur_clock, target_clk, target_vol);
ret = gpu_update_cur_level(platform);
#ifdef CONFIG_EXYNOS_CL_DVFS_G3D
if (!platform->voltage_margin && platform->cl_dvfs_start_base
&& platform->cur_clock >= platform->cl_dvfs_start_base)
exynos7420_cl_dvfs_start(ID_G3D);
#endif
GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "pending clk[%d -> %d], vol[%d (margin : %d)]\n",
prev_clk, gpu_get_cur_clock(platform), gpu_get_cur_voltage(platform), platform->voltage_margin);
return ret;
}