/* gpu power clock init */
int sec_gpu_pwr_clk_init(void)
{
int ret = -1;
gpu_voltage_marin = 0;
sec_gpu_top_clock = 480;
gpu_regulator_enable();
ret = gpu_clks_get();
if (ret) {
PVR_DPF((PVR_DBG_ERROR, "gpu_clks_get error[%d]", ret));
return ret;
}
gpu_power_init();
#if defined(CONFIG_ARM_EXYNOS5410_BUS_DEVFREQ)
pm_qos_add_request(&exynos5_g3d_cpu_qos, PM_QOS_CPU_FREQ_MIN, 0);
pm_qos_add_request(&exynos5_g3d_int_qos, PM_QOS_DEVICE_THROUGHPUT, 0);
pm_qos_add_request(&exynos5_g3d_mif_qos, PM_QOS_BUS_THROUGHPUT, 0);
#endif
return ret;
}
int gpu_regulator_init(struct exynos_context *platform)
{
int gpu_voltage = 0;
#if 0
platform->g3d_regulator = regulator_get(NULL, "vdd_g3d");
#endif
if (IS_ERR(platform->g3d_regulator)) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to get regulator, 0x%p\n", __func__, platform->g3d_regulator);
platform->g3d_regulator = NULL;
return -1;
}
if (gpu_regulator_enable(platform) != 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to enable regulator\n", __func__);
platform->g3d_regulator = NULL;
return -1;
}
#if 0
gpu_voltage = get_match_volt(ID_G3D, platform->gpu_dvfs_config_clock*1000);
#else
gpu_voltage = 0;
#endif
if (gpu_voltage == 0)
gpu_voltage = platform->gpu_default_vol;
if (gpu_set_voltage(platform, gpu_voltage) != 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to set voltage [%d]\n", __func__, gpu_voltage);
return -1;
}
GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "regulator initialized\n");
return 0;
}
