static void set_hpll_clk_out_m8b(unsigned int clk)
{
vout_log_info("%s[%d] clk = %d\n", __func__, __LINE__, clk);
vout_cbus_write(HHI_VID_PLL_CNTL2, 0x69c88000);
vout_cbus_write(HHI_VID_PLL_CNTL3, 0xca563823);
vout_cbus_write(HHI_VID_PLL_CNTL4, 0x40238100);
vout_cbus_write(HHI_VID_PLL_CNTL5, 0x00012286);
/* internal LDO share with HPLL & VIID PLL */
vout_cbus_write(HHI_VID2_PLL_CNTL2, 0x430a800);
switch (clk) {
case 2970:
vout_cbus_write(HHI_VID_PLL_CNTL2, 0x69c84000);
vout_cbus_write(HHI_VID_PLL_CNTL3, 0x8a46c023);
vout_cbus_write(HHI_VID_PLL_CNTL4, 0x4123b100);
vout_cbus_write(HHI_VID_PLL_CNTL5, 0x00012385);
vout_cbus_write(HHI_VID_PLL_CNTL, 0x6000043d);
vout_cbus_write(HHI_VID_PLL_CNTL, 0x4000043d);
wait_for_pll_locked(HHI_VID_PLL_CNTL);
h_delay();
/* optimise HPLL VCO 2.97GHz performance */
vout_cbus_write(HHI_VID_PLL_CNTL5, 0x00016385);
vout_cbus_write(HHI_VID_PLL_CNTL2, 0x69c84e00);
break;
case 2160:
vout_cbus_write(HHI_VID_PLL_CNTL2, 0x69c84000);
vout_cbus_write(HHI_VID_PLL_CNTL3, 0x8a46c023);
vout_cbus_write(HHI_VID_PLL_CNTL4, 0x0123b100);
vout_cbus_write(HHI_VID_PLL_CNTL5, 0x12385);
vout_cbus_write(HHI_VID_PLL_CNTL, 0x6001042d);
vout_cbus_write(HHI_VID_PLL_CNTL, 0x4001042d);
wait_for_pll_locked(HHI_VID_PLL_CNTL);
break;
case 1296:
vout_cbus_write(HHI_VID_PLL_CNTL2, 0x59c88000);
vout_cbus_write(HHI_VID_PLL_CNTL3, 0xca49b022);
vout_cbus_write(HHI_VID_PLL_CNTL4, 0x0023b100);
vout_cbus_write(HHI_VID_PLL_CNTL5, 0x00012385);
vout_cbus_write(HHI_VID_PLL_CNTL, 0x600c0436);
vout_cbus_write(HHI_VID_PLL_CNTL, 0x400c0436);
vout_cbus_write(HHI_VID_PLL_CNTL5, 0x00016385);
wait_for_pll_locked(HHI_VID_PLL_CNTL);
break;
default:
vout_log_info("error hpll clk: %d\n", clk);
break;
}
if (clk < 2970)
vout_cbus_write(HHI_VID_PLL_CNTL5,
(vout_cbus_read(HHI_VID_PLL_CNTL5)
& (~(0xf << 12))) | (0x6 << 12));
} /* meson8b */
static void set_hpll_clk_out(unsigned clk)
{
printk("config HPLL\n");
#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON8
printk("%s[%d] clk = %d\n", __func__, __LINE__, clk);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c88000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0xca563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x40238100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00012286);
aml_write_reg32(P_HHI_VID2_PLL_CNTL2, 0x430a800); // internal LDO share with HPLL & VIID PLL
switch(clk){
case 2971: // only for 4k mode
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case 2976: // only for 4k mode with clock*0.999
#endif
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0xce49c022);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4123b100);
aml_set_reg32_bits(P_HHI_VID2_PLL_CNTL2, 1, 16, 1);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00012385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000043d);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000043d);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
h_delay();
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00016385); // optimise HPLL VCO 2.97GHz performance
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
if (clk == 2976)
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84d04); // lower div_frac to get clk*0.999
else
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84e00);
#else
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84e00);
#endif
break;
case 2970: // for 1080p/i 720p mode
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case 2975: // For 1080P/i 720p mode with clock*0.999
#endif
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a46c023);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00012385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000043d);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000043d);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
h_delay();
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00016385); // optimise HPLL VCO 2.97GHz performance
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
if (clk == 2975)
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84d04); // lower div_frac to get clk*0.999
else
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84e00);
#else
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84e00);
#endif
break;
case 2160:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a46c023);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001042d);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001042d);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
case 2058:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c80000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001042a);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001042a);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8cdf4);
break;
case 1600:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60000442);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40000442);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c506);
break;
case 1710:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60000447);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40000447);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c3ac);
break;
case 2130:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c80000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001042c);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001042c);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c74f);
break;
case 2600:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c80000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60010436);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40010436);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c294);
break;
case 2925:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c80000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001043c);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001043c);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8cfb4);
break;
case 2380:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c80000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60010431);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40010431);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c994);
break;
case 1716:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60000447);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40000447);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c7f8);
break;
case 2014:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c8cf55);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60010429);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40010429);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
case 1422:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000043b);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000043b);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c40f);
break;
case 1540:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c2ab);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60000440);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40000440);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case 2161:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84f48);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a46c023);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001042c);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001042c);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
#endif
case 1080:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000042d);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000042d);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case 1081:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8cf48);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000042c);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000042c);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
#endif
case 1296:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c88000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0xca49b022);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0023b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00012385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x600c0436);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x400c0436);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00016385);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
default:
printk("error hpll clk: %d\n", clk);
break;
}
if(clk < 2970)
aml_write_reg32(P_HHI_VID_PLL_CNTL5, (aml_read_reg32(P_HHI_VID_PLL_CNTL5) & (~(0xf << 12))) | (0x6 << 12));
#endif
#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON8B
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c88000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0xca563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x40238100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00012286);
aml_write_reg32(P_HHI_VID2_PLL_CNTL2, 0x430a800); // internal LDO share with HPLL & VIID PLL
switch(clk){
case 2970:
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case 2975: // FOR 1080P/i 720p mode with clock*0.999
#endif
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a46c023);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00012385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000043d);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000043d);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
h_delay();
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00016385); // optimise HPLL VCO 2.97GHz performance
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
if( clk == 2975 )
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84d04); // lower div_frac to get clk*0.999
else
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84e00);
#else
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84e00);
#endif
break;
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case 2161:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84f48);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a46c023);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001042c);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001042c);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
#endif
case 2160:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a46c023);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001042d);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001042d);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
case 1296:
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c88000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0xca49b022);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0023b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00012385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x600c0436);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x400c0436);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00016385);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
case 1422: /* VMODE_800P */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000043b);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000043b);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c40f);
break;
case 2380: /* VMODE_800X480P_60HZ */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c80000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60010431);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40010431);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c994);
break;
case 1716: /* VMODE_1366X768P_60HZ */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60000447);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40000447);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c7f8);
break;
case 1600: /* VMODE_800X600P_60HZ */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60000442);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40000442);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c506);
break;
case 2058: /* VMODE_1024X600P_60HZ */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c80000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001042a);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001042a);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8cdf4);
break;
case 2600: /* VMODE_1024X768P_60HZ */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c80000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60010436);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40010436);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c294);
break;
case 1710: /* VMODE_1360X768P_60HZ */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60000447);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40000447);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c3ac);
break;
case 2130: /* VMODE_1440X900P_60HZ */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c80000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001042c);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001042c);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c74f);
break;
case 2925: /* VMODE_1680X1050P_60HZ */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c80000);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001043c);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001043c);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8cfb4);
break;
case 1540: /* VMODE_1920x1200 */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c2ab);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60000440);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40000440);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
case 2014: /* VMODE_VGA */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c8cf55);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x60010429);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40010429);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
case 1058: /* VMODE_SVGA */
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x422);
break;
case 1086: /* VMODE_XGA */
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x43e);
break;
case 1080: /* VMODE_SXGA */
aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000);
aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000042d);
aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000042d);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
default:
printk("error hpll clk: %d\n", clk);
break;
}
if(clk < 2970)
aml_write_reg32(P_HHI_VID_PLL_CNTL5, (aml_read_reg32(P_HHI_VID_PLL_CNTL5) & (~(0xf << 12))) | (0x6 << 12));
#endif
#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
printk("%s[%d] clk = %d\n", __func__, __LINE__, clk);
switch(clk){
case 1488:
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x43e);
break;
case 1080:
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x42d);
break;
case 1066:
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x42a);
break;
case 1058:
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x422);
break;
case 1086:
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x43e);
break;
case 1296:
break;
default:
printk("error hpll clk: %d\n", clk);
break;
}
#endif
#if defined(CONFIG_MACH_MESON8B_ODROIDC)
/* Improve HDMI HPLL Long TIE
* 1296MHz is only for 480cvbs/576cvbs on m8 serials
* and is not suitable with 0x8a56d023
*
* http://forum.odroid.com/viewtopic.php?f=117&t=15860&p=104507#p104507
*/
if (voutmode_vga() && clk != 1296)
aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a56d023);
#endif
printk("config HPLL done\n");
}
static void set_hpll_clk_out(unsigned clk)
{
printf("config HPLL\n");
aml_write_reg32_op(P_HHI_VID_PLL_CNTL2, 0x69c88000);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL3, 0xca563823);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL4, 0x40238100);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL5, 0x00012286);
aml_write_reg32_op(P_HHI_VID2_PLL_CNTL2, 0x430a800); // internal LDO share with HPLL & VIID PLL
aml_write_reg32_op(P_HHI_HDMI_PHY_CNTL0, 0x08c31e8b);
switch(clk){
case 2970:
aml_write_reg32_op(P_HHI_VID_PLL_CNTL2, 0x69c84000);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL3, 0x8a46c023);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL4, 0x4123b100);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL5, 0x00012385);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x6000043d);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x4000043d);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
h_delay();
aml_write_reg32_op(P_HHI_VID_PLL_CNTL5, 0x00016385); // optimise HPLL VCO 2.97GHz performance
aml_write_reg32_op(P_HHI_VID_PLL_CNTL2, 0x69c84e00);
break;
case 2160:
aml_write_reg32_op(P_HHI_VID_PLL_CNTL2, 0x69c84000);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL3, 0x8a46c023);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x6001042d);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x4001042d);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
break;
case 1488:
aml_write_reg32_op(P_HHI_VID_PLL_CNTL2, 0x69c8c000);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x6000043d);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x4000043d);
WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL2, 0x69c8ce00);
break;
case 1296:
aml_write_reg32_op(P_HHI_VID_PLL_CNTL2, 0x59c88000);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL3, 0xca49b022);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL4, 0x0023b100);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL5, 0x00012385);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x600c0436);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x400c0436);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL5, 0x00016385);
break;
default:
printf("error hpll clk: %d\n", clk);
break;
}
if(clk < 2970)
aml_write_reg32_op(P_HHI_VID_PLL_CNTL5, (aml_read_reg32_op(P_HHI_VID_PLL_CNTL5) & (~(0xf << 12))) | (0x6 << 12));
// P_HHI_HDMI_PHY_CNTL1 bit[1]: enable clock bit[0]: soft reset
#define RESET_HDMI_PHY() \
aml_write_reg32_op(P_HHI_HDMI_PHY_CNTL1, 3); \
h_delay(); \
aml_write_reg32_op(P_HHI_HDMI_PHY_CNTL1, 2); \
h_delay()
RESET_HDMI_PHY();
RESET_HDMI_PHY();
RESET_HDMI_PHY();
printf("config HPLL done\n");
}
static void set_hpll_clk_out(unsigned clk)
{
aml_write_reg32_op(P_HHI_VID_PLL_CNTL2, 0x69c88000);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL3, 0xca563823);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL4, 0x40238100);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL5, 0x00012286);
aml_write_reg32_op(P_HHI_VID2_PLL_CNTL2, 0x430a800); // internal LDO share with HPLL & VIID PLL
switch(clk){
case 2970:
aml_write_reg32_op(P_HHI_VID_PLL_CNTL2, 0x59c84e00);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL3, 0xce49c822);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL4, 0x4123b100);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL5, 0x00012385);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x6000043d);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x4000043d);
printf("waiting HPLL lock\n");
while(!(aml_read_reg32_op(P_HHI_VID_PLL_CNTL) & (1 << 31))) {
;
}
h_delay();
aml_write_reg32_op(P_HHI_VID_PLL_CNTL5, 0x00016385); // optimise HPLL VCO 2.97GHz performance
break;
case 2160:
aml_write_reg32_op(P_HHI_VID_PLL_CNTL2, 0x59c80000);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL3, 0x0a563823);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL4, 0x0123b100);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL5, 0x12385);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x6001042d);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x4001042d);
while(!(aml_read_reg32_op(P_HHI_VID_PLL_CNTL) & (1 << 31))) {
;
}
break;
case 1488:
aml_write_reg32_op(P_HHI_VID_PLL_CNTL2, 0x69c8ce00);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL4, 0x4023d100);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL3, 0x8a7ad023);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL5, 0x12286);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x6000043d);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x4000043d);
while(!(aml_read_reg32_op(P_HHI_VID_PLL_CNTL) & (1 << 31))) {
;
}
break;
case 1080:
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x6000042d);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x4000042d);
break;
case 1066:
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x42a);
break;
case 1058:
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x422);
break;
case 1086:
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x43e);
break;
case 1296:
aml_write_reg32_op(P_HHI_VID_PLL_CNTL2, 0x59c88000);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL3, 0xca49b022);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL4, 0x0023b100);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL5, 0x00012385);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x600c0436);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL, 0x400c0436);
aml_write_reg32_op(P_HHI_VID_PLL_CNTL5, 0x00016385);
break;
default:
printf("error hpll clk: %d\n", clk);
break;
}
if(clk < 2970)
aml_write_reg32_op(P_HHI_VID_PLL_CNTL5, (aml_read_reg32_op(P_HHI_VID_PLL_CNTL5) & (~(0xf << 12))) | (0x6 << 12));
// Improve HDMI HPLL Long TIE
if( clk != 1296 ) // 1296MHz is only for 480cvbs/576cvbs on m8 serials, and is not suitable with 0x8a56d023
aml_write_reg32_op(P_HHI_VID_PLL_CNTL3, 0x8a56d023);
}
