/* Radio "interrupt" routine.
* (but it is only manually called) */
void nrf_irq()
{
uint8_t irq_flags;
// Read and clear IRQ flags from radio.
irq_flags = hal_nrf_get_clear_irq_flags();
switch (irq_flags) {
// Transmission success
case (1 << (uint8_t)HAL_NRF_TX_DS):
send_success = true;
// Data has been sent
break;
// Transmission failed (maximum re-transmits)
case (1 << (uint8_t)HAL_NRF_MAX_RT):
hal_nrf_flush_tx();
send_success = false;
break;
// Data received
case (1 << (uint8_t)HAL_NRF_RX_DR):
// Read payload
while (!hal_nrf_rx_fifo_empty()) {
hal_nrf_read_rx_payload(rcvd_buf);
}
packet_received = true;
break;
default:
;
}
}
void epl_dbg_init()
{
//Start RF tx mode
epl_rf_en_quick_init(cfg);
//epl_rf_en_enter_tx_mode();
//test
epl_uart_init(UART_BAUD_57K6);
//Clear TX FIFO
hal_nrf_flush_tx();
}
void hal_nrf_set_sta(hal_nrf_sta_t sta)
{
u8 len, i;
if(hal_nrf_tx_cnt){
hal_nrf_tx_cmd_flag = 0;
HAL_NRF_WAIT_ACK_DONE();
IRQ_DIS();
CE_LOW();
hal_nrf_flush_tx();
hal_nrf_flush_rx();
hal_nrf_sta = HAL_NRF_STA_TX;
hal_nrf_tx_busy = 1;
len = hal_nrf_tx_buf[hal_nrf_tx_rd_index];
hal_nrf_tx_rd_index++;
if(hal_nrf_tx_rd_index == HAL_NRF_TX_BUF_LEN){
hal_nrf_tx_rd_index = 0;
}
hal_nrf_tx_cnt = hal_nrf_tx_cnt-len-1;
// hal_nrf_write_tx_payload(hal_nrf_tx_buf_tmp, len);
CSN_LOW();
HAL_NRF_HW_SPI_WRITE(W_TX_PAYLOAD);
while(HAL_NRF_HW_SPI_BUSY) {}
HAL_NRF_HW_SPI_READ();
for(i=0; i<len; i++){
HAL_NRF_HW_SPI_WRITE(hal_nrf_tx_buf[hal_nrf_tx_rd_index]);
hal_nrf_tx_rd_index++;
if(hal_nrf_tx_rd_index == HAL_NRF_TX_BUF_LEN){
hal_nrf_tx_rd_index = 0;
}
while(HAL_NRF_HW_SPI_BUSY) {} /* wait for byte transfer finished */
HAL_NRF_HW_SPI_READ();
}
CSN_HIGH();
hal_nrf_set_operation_mode(HAL_NRF_PTX);
// CE_HIGH();
// T2_START();
t2_start_delay();
IRQ_EN();
}else{
read_flash_buf(slave_cmd, slave_cmd_end, CMD_LENGTH);
hal_nrf_send_cmd(slave_cmd, HAL_NRF_STA_RX);
hal_nrf_tx_cmd_flag = 2;
}
}
void hal_nrf_send_cmd(u8 *buf, u8 sta)
{
/** auto ack delay */
HAL_NRF_WAIT_ACK_DONE();
IRQ_DIS();
CE_LOW();
hal_nrf_flush_tx();
hal_nrf_flush_rx();
hal_nrf_sta = HAL_NRF_STA_TX_CMD;
// hal_nrf_sta_next = sta;
hal_nrf_write_tx_payload(buf, CMD_LENGTH);
// hal_nrf_write_tx_payload_noack(buf, CMD_LENGTH);
hal_nrf_set_operation_mode(HAL_NRF_PTX);
// CE_HIGH();
// T2_START();
t2_start_delay();
IRQ_EN();
}
void radio_irq(void)
{
if (RADIO_ACTIVITY()) // Check if an interupt is
{ // triggered
switch(hal_nrf_get_clear_irq_flags ())
{
case (1<<HAL_NRF_MAX_RT): // Max retries reached
hal_nrf_flush_tx(); // flush tx fifo, avoid fifo jam
radio_set_status (RF_MAX_RT);
break;
case (1<<HAL_NRF_TX_DS): // Packet sent
radio_set_status (RF_TX_DS);
break;
case (1<<HAL_NRF_RX_DR): // Packet received
while (!hal_nrf_rx_fifo_empty ())
{
hal_nrf_read_rx_pload(pload);
}
radio_set_status (RF_RX_DR);
break;
case ((1<<HAL_NRF_RX_DR)|(1<<HAL_NRF_TX_DS)): // Ack payload recieved
while (!hal_nrf_rx_fifo_empty ())
{
hal_nrf_read_rx_pload(pload);
}
radio_set_status (RF_TX_AP);
break;
default:
break;
}
RESET_RADIO_ACTIVITY();
}
}
__interrupt void HAL_NRF_ISR(void)
{
u8 status, len, i;
if(!IRQ) {
/** */
// Read and clear IRQ flags from radio
status = hal_nrf_nop();
// if(hal_nrf_ack_flag){
// if((status&0x60) == 0x60){
// hal_nrf_ack_flag = 0;
// }else{
// read_flash_buf(slave_cmd, slave_cmd_request, CMD_LENGTH);
// hal_nrf_write_ack_payload(0, slave_cmd, CMD_LENGTH);
// }
// }
#ifdef SLAVE_DEBUG
hal_nrf_irq_flag = status;
#endif
if(status & (1<< (uint8_t)HAL_NRF_RX_DR)){
do{
len = hal_nrf_read_rx_payload_width();
if(len > 32){
hal_nrf_write_reg (STATUS, (1<< (uint8_t)HAL_NRF_RX_DR));
hal_nrf_rx_sta = HAL_NRF_RX_STA_COM_ERROR;
return;
}
if((hal_nrf_rx_cnt + len + 1) < HAL_NRF_RX_BUF_LEN){
hal_nrf_rx_buf[hal_nrf_rx_wr_index] = len;
hal_nrf_rx_wr_index++;
if(hal_nrf_rx_wr_index == HAL_NRF_RX_BUF_LEN){
hal_nrf_rx_wr_index=0;
}
// hal_nrf_read_payload((u8*)hal_nrf_rx_buf[hal_nrf_rx_wr_index].buf, len);
CSN_LOW();
HAL_NRF_HW_SPI_WRITE(R_RX_PAYLOAD);
while(HAL_NRF_HW_SPI_BUSY) {}
HAL_NRF_HW_SPI_READ();
for(i=0; i<len; i++){
HAL_NRF_HW_SPI_WRITE(0U);
while(HAL_NRF_HW_SPI_BUSY){}
hal_nrf_rx_buf[hal_nrf_rx_wr_index] = HAL_NRF_HW_SPI_READ();
hal_nrf_rx_wr_index++;
if(hal_nrf_rx_wr_index == HAL_NRF_RX_BUF_LEN){
hal_nrf_rx_wr_index=0;
}
}
CSN_HIGH();
hal_nrf_rx_cnt = hal_nrf_rx_cnt+len+1;
}else{
hal_nrf_flush_rx();
hal_nrf_rx_sta = HAL_NRF_RX_STA_BUF_OVF;
/** clear RX_DR */
hal_nrf_write_reg (STATUS, (1<< (uint8_t)HAL_NRF_RX_DR));
break;
}
/** clear RX_DR */
hal_nrf_write_reg (STATUS, (1<< (uint8_t)HAL_NRF_RX_DR));
}while(!hal_nrf_rx_fifo_empty());
}
if(status & (1 << (uint8_t)HAL_NRF_TX_DS)){
hal_nrf_write_reg (STATUS, (1<< (uint8_t)HAL_NRF_TX_DS));
switch(hal_nrf_sta){
case HAL_NRF_STA_TX:
hal_nrf_tx_cmd_flag = 0;
if(hal_nrf_tx_cnt){
hal_nrf_tx_busy = 1;
len = hal_nrf_tx_buf[hal_nrf_tx_rd_index];
hal_nrf_tx_rd_index++;
if(hal_nrf_tx_rd_index == HAL_NRF_TX_BUF_LEN){
hal_nrf_tx_rd_index = 0;
}
hal_nrf_tx_cnt = hal_nrf_tx_cnt-len-1;
// hal_nrf_write_tx_payload(hal_nrf_tx_buf_tmp, len);
CSN_LOW();
HAL_NRF_HW_SPI_WRITE(W_TX_PAYLOAD);
while(HAL_NRF_HW_SPI_BUSY) {}
HAL_NRF_HW_SPI_READ();
for(i=0; i<len; i++){
HAL_NRF_HW_SPI_WRITE(hal_nrf_tx_buf[hal_nrf_tx_rd_index]);
hal_nrf_tx_rd_index++;
if(hal_nrf_tx_rd_index == HAL_NRF_TX_BUF_LEN){
hal_nrf_tx_rd_index = 0;
}
while(HAL_NRF_HW_SPI_BUSY) {} /* wait for byte transfer finished */
HAL_NRF_HW_SPI_READ();
}
CSN_HIGH();
// CE_HIGH();
// T2_START();
t2_start_delay();
}else{
if(hal_nrf_tx_sta == HAL_NRF_TX_STA_IDLE){
/** send end pkt */
hal_nrf_tx_sta = HAL_NRF_TX_STA_DONE;
read_flash_buf(slave_cmd, slave_cmd_end, CMD_LENGTH);
hal_nrf_write_tx_payload(slave_cmd, CMD_LENGTH);
hal_nrf_tx_cmd_flag = 2;
// CE_HIGH();
// T2_START();
t2_start_delay();
}else{
hal_nrf_tx_sta = HAL_NRF_TX_STA_IDLE;
hal_nrf_sta = HAL_NRF_STA_RX;
CE_LOW();
hal_nrf_flush_tx();
hal_nrf_flush_rx();
/** return to RX mode */
hal_nrf_set_operation_mode(HAL_NRF_PRX);
CE_HIGH();
hal_nrf_tx_busy = 0;
}
}
break;
case HAL_NRF_STA_RX:
/** ack payload send */
break;
case HAL_NRF_STA_TX_CMD:
hal_nrf_sta = HAL_NRF_STA_RX;
CE_LOW();
hal_nrf_flush_tx();
hal_nrf_flush_rx();
/** return to RX mode */
hal_nrf_set_operation_mode(HAL_NRF_PRX);
CE_HIGH();
hal_nrf_tx_busy = 0;
hal_nrf_tx_cmd_flag = 0;
break;
}
}
if(status & (1 << (uint8_t)HAL_NRF_MAX_RT)){
#if 0
// When a MAX_RT interrupt occurs the TX payload will not be removed from the TX FIFO.
// If the packet is to be discarded this must be done manually by flushing the TX FIFO.
// Alternatively, CE_PULSE() can be called re-starting transmission of the payload.
// (Will only be possible after the radio irq flags are cleared)
hal_nrf_flush_tx();
hal_nrf_flush_rx();
hal_nrf_set_operation_mode(HAL_NRF_PRX);
CE_HIGH();
hal_nrf_sta=HAL_NRF_STA_RX;
/** discard all data in buffer */
hal_nrf_tx_busy = 0;
hal_nrf_tx_cnt = 0;
hal_nrf_tx_rd_index =0;
hal_nrf_tx_wr_index = 0;
// hal_nrf_flush_rx();
// hal_nrf_rx_cnt = 0;
// hal_nrf_rx_rd_index =0;
// hal_nrf_rx_wr_index = 0;
/** set timeout flag */
hal_nrf_timeout = 1;
hal_nrf_write_reg (STATUS, (1<< (uint8_t)HAL_NRF_MAX_RT));
#else
hal_nrf_write_reg (STATUS, (1<< (uint8_t)HAL_NRF_MAX_RT));
switch(hal_nrf_sta){
case HAL_NRF_STA_TX:
hal_nrf_tx_cmd_flag = 0;
if(hal_nrf_tx_cnt){
hal_nrf_tx_busy = 1;
len = hal_nrf_tx_buf[hal_nrf_tx_rd_index];
hal_nrf_tx_rd_index++;
if(hal_nrf_tx_rd_index == HAL_NRF_TX_BUF_LEN){
hal_nrf_tx_rd_index = 0;
}
hal_nrf_tx_cnt = hal_nrf_tx_cnt-len-1;
// hal_nrf_write_tx_payload(hal_nrf_tx_buf_tmp, len);
CSN_LOW();
HAL_NRF_HW_SPI_WRITE(W_TX_PAYLOAD);
while(HAL_NRF_HW_SPI_BUSY) {}
HAL_NRF_HW_SPI_READ();
for(i=0; i<len; i++){
HAL_NRF_HW_SPI_WRITE(hal_nrf_tx_buf[hal_nrf_tx_rd_index]);
hal_nrf_tx_rd_index++;
if(hal_nrf_tx_rd_index == HAL_NRF_TX_BUF_LEN){
hal_nrf_tx_rd_index = 0;
}
while(HAL_NRF_HW_SPI_BUSY) {} /* wait for byte transfer finished */
HAL_NRF_HW_SPI_READ();
}
CSN_HIGH();
// CE_HIGH();
// T2_START();
t2_start_delay();
}else{
if(hal_nrf_tx_sta == HAL_NRF_TX_STA_IDLE){
/** send end pkt */
hal_nrf_tx_sta = HAL_NRF_TX_STA_DONE;
read_flash_buf(slave_cmd, slave_cmd_end, CMD_LENGTH);
hal_nrf_write_tx_payload(slave_cmd, CMD_LENGTH);
hal_nrf_tx_cmd_flag = 2;
// CE_HIGH();
// T2_START();
t2_start_delay();
}else{
hal_nrf_tx_sta = HAL_NRF_TX_STA_IDLE;
hal_nrf_sta = HAL_NRF_STA_RX;
CE_LOW();
hal_nrf_flush_tx();
hal_nrf_flush_rx();
/** return to RX mode */
hal_nrf_set_operation_mode(HAL_NRF_PRX);
CE_HIGH();
hal_nrf_tx_busy = 0;
}
}
break;
case HAL_NRF_STA_RX:
/** ack payload send */
break;
case HAL_NRF_STA_TX_CMD:
hal_nrf_sta = HAL_NRF_STA_RX;
CE_LOW();
hal_nrf_flush_tx();
hal_nrf_flush_rx();
/** return to RX mode */
hal_nrf_set_operation_mode(HAL_NRF_PRX);
CE_HIGH();
hal_nrf_tx_busy = 0;
hal_nrf_tx_cmd_flag = 0;
break;
}
#endif
}
}
}
bool gzll_tx_data(const uint8_t *src, uint8_t length, uint8_t pipe)
{
uint8_t temp_address[GZLL_ADDRESS_WIDTH];
uint16_t temp;
uint32_t flag;
ASSERT(length <= GZLL_MAX_FW_PAYLOAD_LENGTH && length > 0);
ASSERT(pipe <= 5);
/*
Length check to prevent memory corruption. (Note, assertion
will capture this as well).
*/
if(length == 0 || length > GZLL_MAX_FW_PAYLOAD_LENGTH)
{
return false;
}
gzll_current_tx_payload_length = length;
if(gzll_state_var == GZLL_HOST_ACTIVE)
{
gzll_goto_idle();
}
flag = gzll_interupts_save();
/*
If the specified pipe is different from the previous TX pipe,
the TX setup must be updated
*/
if(pipe != gzll_current_tx_pipe)
{
gzll_current_tx_pipe = pipe;
gzll_tx_setup_modified = true;
}
/*
Here, state can be GZLL_IDLE or GZLL_DEVICE_ACTIVE
*/
if(gzll_state_var == GZLL_IDLE)
{
if(gzll_tx_setup_modified) // TX setup has to be restored?
{
gzll_tx_setup_modified = false;
gzll_rx_setup_modified = true;
hal_nrf_set_operation_mode(HAL_NRF_PTX);
hal_nrf_open_pipe(HAL_NRF_PIPE0, EN_AA);
//Read out the full RX address for pipe number "pipe"
if(pipe == HAL_NRF_PIPE0)
{
hal_nrf_set_address(HAL_NRF_TX, gzll_p0_adr);
hal_nrf_set_address(HAL_NRF_PIPE0, gzll_p0_adr);
}
else
{
//lint -esym(550,bytes_in_buffer) "variable not accessed"
//lint -esym(438,bytes_in_buffer) "last assigned value not used"
uint8_t bytes_in_buffer;
bytes_in_buffer = hal_nrf_get_address(HAL_NRF_PIPE1, temp_address);
if(pipe != HAL_NRF_PIPE1)
{
switch(pipe)
{
default:
case HAL_NRF_PIPE2:
bytes_in_buffer = hal_nrf_get_address(HAL_NRF_PIPE2, temp_address);
break;
case HAL_NRF_PIPE3:
bytes_in_buffer = hal_nrf_get_address(HAL_NRF_PIPE3, temp_address);
break;
case HAL_NRF_PIPE4:
bytes_in_buffer = hal_nrf_get_address(HAL_NRF_PIPE4, temp_address);
break;
case HAL_NRF_PIPE5:
bytes_in_buffer = hal_nrf_get_address(HAL_NRF_PIPE5, temp_address);
break;
}
bytes_in_buffer = bytes_in_buffer;
}
//Here, temp_address will contain the full TX address
hal_nrf_set_address(HAL_NRF_PIPE0, temp_address);
hal_nrf_set_address(HAL_NRF_TX, temp_address);
/*
Change seed for random generator. Will prevent different devices
transmitting to the same host from using the same channel hopping
sequence.
*/
//lint -esym(534, gzll_lfsr_get) "return value ignored"
gzll_lfsr_get(pipe, 1);
}
}
// Prepare for new transmission
gzll_timeout_counter = 0;
gzll_channel_switch_counter = 0;
gzll_try_counter = 0;
hal_nrf_flush_tx();
GZLL_UPLOAD_PAYLOAD_TO_RADIO();
gzll_tx_success_f = false; // Transmission by default "failure"
temp = gzll_dyn_params[GZLL_PARAM_DEVICE_MODE];
gzll_set_radio_power_on(true);
if(gzll_sync_on)
{
switch(temp)
{
case GZLL_DEVICE_MODE_2:
default:
gzll_start_new_tx(GZLL_CHANNEL_PREVIOUS_SUCCESS);
break;
case GZLL_DEVICE_MODE_3:
gzll_start_new_tx(GZLL_CHANNEL_RANDOM);
break;
case GZLL_DEVICE_MODE_4:
gzll_start_new_tx(GZLL_CHANNEL_ESTIMATED);
break;
}
}
else
{
switch(temp)
{
case GZLL_DEVICE_MODE_0:
case GZLL_DEVICE_MODE_2:
gzll_start_new_tx(GZLL_CHANNEL_PREVIOUS_SUCCESS);
break;
default:
gzll_start_new_tx(GZLL_CHANNEL_RANDOM);
break;
}
}
gzll_state_var = GZLL_DEVICE_ACTIVE;
gzll_interupts_restore(flag);
return true; // Payload successfully written to TX FIFO
}
else // Else TRANSMIT state
{
/*
Check if criteria for starting new transmission when already transmitting
is fulfilled
*/
if(!gzll_tx_setup_modified &&
!hal_nrf_tx_fifo_full()
)
{
GZLL_UPLOAD_PAYLOAD_TO_RADIO();
gzll_interupts_restore(flag);
return true; // Payload successfully written to TX FIFO
}
else
{
gzll_interupts_restore(flag);
return false; // Payload not written to TX FIFO
}
}
}
void gzll_init(void)
{
uint32_t flag;
uint8_t temp_adr[GZLL_ADDRESS_WIDTH] = GZLL_DEFAULT_ADDRESS_PIPE1;
flag = gzll_interupts_save();
GZLL_RFCE_LOW();
hal_nrf_enable_ack_payload(true);
hal_nrf_enable_dynamic_payload(true);
hal_nrf_setup_dynamic_payload(0xff);
/*
Initialize status variables.
*/
gzll_channel_tab_index = 0;
gzll_channel_tab_size = GZLL_DEFAULT_CHANNEL_TAB_SIZE;
gzll_pending_goto_idle = false;
gzll_timer_period_modified = false;
gzll_current_tx_pipe = 0;
gzll_pending_tx_start = false;
gzll_tx_setup_modified = true;
gzll_rx_setup_modified = true;
gzll_radio_active_f = false;
gzll_tx_success_f = true;
gzll_sync_period = 0;
gzll_sync_on = false;
gzll_rx_dr = false;
gzll_rx_power_high_f = false;
gzll_ack_rx_pipe_fifo_cnt = 0;
/*
Set up default addresses.
*/
hal_nrf_set_address(HAL_NRF_PIPE0, gzll_p0_adr);
hal_nrf_set_address(HAL_NRF_PIPE1, temp_adr);
temp_adr[0] = GZLL_DEFAULT_ADDRESS_PIPE2;
hal_nrf_set_address(HAL_NRF_PIPE2, temp_adr);
temp_adr[0] = GZLL_DEFAULT_ADDRESS_PIPE3;
hal_nrf_set_address(HAL_NRF_PIPE3, temp_adr);
temp_adr[0] = GZLL_DEFAULT_ADDRESS_PIPE4;
hal_nrf_set_address(HAL_NRF_PIPE4, temp_adr);
temp_adr[0] = GZLL_DEFAULT_ADDRESS_PIPE5;
hal_nrf_set_address(HAL_NRF_PIPE5, temp_adr);
/*
Set up default channel.
*/
hal_nrf_set_rf_channel(gzll_channel_tab[gzll_channel_tab_index]);
/*
Initialize dynamic parameters using default values.
*/
gzll_dyn_params[GZLL_PARAM_DEVICE_MODE] = GZLL_DEFAULT_PARAM_DEVICE_MODE;
gzll_dyn_params[GZLL_PARAM_TX_TIMEOUT] = GZLL_DEFAULT_PARAM_TX_TIMEOUT;
gzll_dyn_params[GZLL_PARAM_TX_ATTEMPTS_PR_CHANNEL_WHEN_SYNC_ON] = GZLL_DEFAULT_PARAM_TX_ATTEMPTS_PR_CHANNEL_WHEN_SYNC_ON;
gzll_dyn_params[GZLL_PARAM_TX_ATTEMPTS_PR_CHANNEL_WHEN_SYNC_OFF] = GZLL_DEFAULT_PARAM_TX_ATTEMPTS_PR_CHANNEL_WHEN_SYNC_OFF;
gzll_dyn_params[GZLL_PARAM_HOST_MODE] = GZLL_DEFAULT_PARAM_HOST_MODE;
gzll_dyn_params[GZLL_PARAM_RX_PIPES] = GZLL_DEFAULT_PARAM_RX_PIPES;
gzll_dyn_params[GZLL_PARAM_CRYPT_PIPES] = GZLL_DEFAULT_PARAM_CRYPT_PIPES;
gzll_dyn_params[GZLL_PARAM_RX_TIMEOUT] = GZLL_DEFAULT_PARAM_RX_TIMEOUT;
gzll_dyn_params[GZLL_PARAM_HOST_MODE_1_CYCLE_PERIOD] = GZLL_DEFAULT_PARAM_HOST_MODE_1_CYCLE_PERIOD;
gzll_dyn_params[GZLL_PARAM_RX_PERIOD] = GZLL_DEFAULT_PARAM_RX_PERIOD;
gzll_dyn_params[GZLL_PARAM_RX_PERIOD_MODIFIER] = GZLL_DEFAULT_PARAM_RX_PERIOD_MODIFIER;
gzll_dyn_params[GZLL_PARAM_RX_CHANNEL_HOLD_PERIODS] = GZLL_DEFAULT_PARAM_RX_CHANNEL_HOLD_PERIODS;
gzll_dyn_params[GZLL_PARAM_OUTPUT_POWER] = GZLL_DEFAULT_PARAM_OUTPUT_POWER;
gzll_dyn_params[GZLL_PARAM_POWER_DOWN_IDLE_ENABLE] = GZLL_DEFAULT_PARAM_POWER_DOWN_IDLE_ENABLE;
gzll_dyn_params[GZLL_PARAM_MAX_SYNC_PERIOD] = GZLL_DEFAULT_PARAM_MAX_SYNC_PERIOD;
gzll_dyn_params[GZLL_PARAM_COLLISION_CHANNEL_SWITCH_LIMIT] = GZLL_DEFAULT_PARAM_COLLISION_CHANNEL_SWITCH_LIMIT;
/*
Set up default output power.
*/
hal_nrf_set_output_power((hal_nrf_output_power_t) gzll_dyn_params[GZLL_PARAM_OUTPUT_POWER]);
/*
Static radio setup.
*/
hal_nrf_set_datarate(GZLL_HAL_DATARATE);
hal_nrf_set_crc_mode(GZLL_CRC);
hal_nrf_set_address_width(GZLL_ADDRESS_WIDTH);
/*
Clear radio IRQ flags.
*/
//lint -esym(534, hal_nrf_get_clear_irq_flags) "return value ignored"
hal_nrf_get_clear_irq_flags();
hal_nrf_flush_rx();
hal_nrf_flush_tx();
gzll_set_timer_period(GZLL_DEFAULT_PARAM_RX_PERIOD);
gzll_set_system_idle();
gzll_interupts_restore(flag);
}
