/**
* @brief Initializes the transceiver
*
* This function is called to initialize the transceiver.
*
* @return MAC_SUCCESS if the transceiver state is changed to TRX_OFF and the
* current device part number and version number are correct;
* FAILURE otherwise
*/
static uint8_t trx_init(void)
{
uint8_t trx_status;
uint8_t poll_counter = 0;
hal_set_rst_high();
hal_set_slptr_low();
/* Wait typical time of timer TR1. */
delay_us(P_ON_TO_CLKM_AVAILABLE_TYP_US);
/* Apply reset pulse */
hal_set_rst_low();
delay_us(RST_PULSE_WIDTH_US);
hal_set_rst_high();
/* Verify that TRX_OFF can be written */
do
{
/* Wait not more than max. value of TR1. */
if (poll_counter == P_ON_TO_CLKM_ATTEMPTS)
{
return(-1/* FAILURE*/);
}
/* Wait a short time interval. */
delay_us(TRX_POLL_WAIT_TIME_US);
poll_counter++;
/* Check if AT86RF231 is connected; omit manufacturer id check */
} while ((hal_register_read(RG_VERSION_NUM) != AT86RF231_VERSION_NUM) ||
(hal_register_read(RG_PART_NUM) != AT86RF231_PART_NUM));
/* Verify that TRX_OFF can be written */
hal_register_write(RG_TRX_STATE, CMD_TRX_OFF);
/* Verify that the trx has reached TRX_OFF. */
poll_counter = 0;
do
{
/* Wait a short time interval. */
delay_us(TRX_POLL_WAIT_TIME_US);
trx_status = (uint8_t)hal_subregister_read(SR_TRX_STATUS);
/* Wait not more than max. value of TR2. */
if (poll_counter == SLEEP_TO_TRX_OFF_ATTEMPTS)
{
return(-1/* FAILURE*/);
}
poll_counter++;
} while (trx_status != TRX_OFF);
tal_trx_status = TRX_OFF;
return(0);
}
U8 drvr_get_cca()
{
return hal_subregister_read(SR_CCA_MODE);
}
bool drvr_get_coord()
{
return hal_subregister_read(SR_I_AM_COORD);
}
U8 drvr_get_tx_pwr()
{
return hal_subregister_read(SR_TX_PWR);
}
U8 drvr_get_channel()
{
return hal_subregister_read(SR_CHANNEL);
}
U8 drvr_get_trx_state()
{
return hal_subregister_read(SR_TRX_STATUS);
}
/*---------------------------------------------------------------------------*/
int
nrf24l01_read(void *buf, unsigned short bufsize)
{
uint8_t *framep;
// uint8_t footer[2];
uint8_t len;
#if RF230_CONF_CHECKSUM
uint16_t checksum;
#endif /* RF230_CONF_CHECKSUM */
#if RF230_CONF_TIMESTAMPS
struct timestamp t;
#endif /* RF230_CONF_TIMESTAMPS */
PRINTF("rf230_read: %u bytes lqi %u crc %u\n",rxframe.length,rxframe.lqi,rxframe.crc);
#if DEBUG>1
for (len=0;len<rxframe.length;len++) PRINTF(" %x",rxframe.data[len]);PRINTF("\n");
#endif
if (rxframe.length==0) {
return 0;
}
#if RF230_CONF_TIMESTAMPS
bomb
if(interrupt_time_set) {
rf230_time_of_arrival = interrupt_time;
interrupt_time_set = 0;
} else {
rf230_time_of_arrival = 0;
}
rf230_time_of_departure = 0;
#endif /* RF230_CONF_TIMESTAMPS */
GET_LOCK();
// if(rxframe.length > RF230_MAX_PACKET_LEN) {
// // Oops, we must be out of sync.
// flushrx();
// RIMESTATS_ADD(badsynch);
// RELEASE_LOCK();
// return 0;
// }
//hal returns two extra bytes containing the checksum
//below works because auxlen is 2
len = rxframe.length;
if(len <= AUX_LEN) {
// flushrx();
RIMESTATS_ADD(tooshort);
RELEASE_LOCK();
return 0;
}
if(len - AUX_LEN > bufsize) {
// flushrx();
RIMESTATS_ADD(toolong);
RELEASE_LOCK();
return 0;
}
/* Transfer the frame, stripping the checksum */
framep=&(rxframe.data[0]);
memcpy(buf,framep,len-2);
/* Clear the length field to allow buffering of the next packet */
rxframe.length=0;
// framep+=len-AUX_LEN+2;
#if RADIOSTATS
RF230_receivepackets++;
#endif
#if RF230_CONF_CHECKSUM
bomb
memcpy(&checksum,framep,CHECKSUM_LEN);
framep+=CHECKSUM_LEN;
#endif /* RF230_CONF_CHECKSUM */
#if RF230_CONF_TIMESTAMPS
bomb
memcpy(&t,framep,TIMESTAMP_LEN);
framep+=TIMESTAMP_LEN;
#endif /* RF230_CONF_TIMESTAMPS */
// memcpy(&footer,framep,FOOTER_LEN);
#if RF230_CONF_CHECKSUM
bomb
if(checksum != crc16_data(buf, len - AUX_LEN, 0)) {
PRINTF("rf230: checksum failed 0x%04x != 0x%04x\n",
checksum, crc16_data(buf, len - AUX_LEN, 0));
}
if(footer[1] & FOOTER1_CRC_OK &&
checksum == crc16_data(buf, len - AUX_LEN, 0)) {
#else
if (rxframe.crc) {
#endif /* RF230_CONF_CHECKSUM */
#if RADIOSTATS
RF230_rsigsi=hal_subregister_read( SR_RSSI );
#endif
//nick packetbuf_set_attr(PACKETBUF_ATTR_RSSI, hal_subregister_read( SR_RSSI ));
//nick packetbuf_set_attr(PACKETBUF_ATTR_LINK_QUALITY, rxframe.lqi);
RIMESTATS_ADD(llrx);
#if RF230_CONF_TIMESTAMPS
bomb
rf230_time_of_departure =
t.time +
setup_time_for_transmission +
(total_time_for_transmission * (len - 2)) / total_transmission_len;
rf230_authority_level_of_sender = t.authority_level;
packetbuf_set_attr(PACKETBUF_ATTR_TIMESTAMP, t.time);
#endif /* RF230_CONF_TIMESTAMPS */
} else {
PRINTF("rf230: Bad CRC\n");
#if RADIOSTATS
RF230_receivefail++;
#endif
RIMESTATS_ADD(badcrc);
len = AUX_LEN;
}
// if (?)
/* Another packet has been received and needs attention. */
// process_poll(&nrf24l01_process);
// }
RELEASE_LOCK();
if(len < AUX_LEN) {
return 0;
}
return len - AUX_LEN;
}
/*---------------------------------------------------------------------------*/
void
nrf24l01_init(uint8_t mode)
{
rf_mode = mode;
/* Initialize Hardware Abstraction Layer. */
//hal_init();
//init the spi functions
spi_init();
SPI_CHIP_ENABLE();
if(RF_TX_MODE == mode) //tx mode
{
SPI_WRITE_REG(WRITE_REG, 0x0C); //RX_DR, TX_DS, MAX_RT interrupts enabled, CRC enabled, CRC encoding with 2bytes and as PTX
//SPI_WRITE_REG(WRITE_REG+EN_AA, 0x3F); //Enable auto-acknowledge for all data pipe
//SPI_WRITE_REG(WRITE_REG+EN_RXADDR, 0x01); //Enable RX address data pipe 0, reset value is 0x03 (data pipe 0 and 1)
//SPI_WRITE_REG(WRITE_REG+SETUP_AW, 0x03); //Setup of address width, reset value is 0x33--5 bytes
SPI_WRITE_REG(WRITE_REG+SETUP_RETR, 0xFF); //Set auto-retransmision, ARD(auto retransmit delay): 1111, ARC(auto retransmit count): 1111
//SPI_WRITE_REG(WRITE_REG+RF_CH, 0x02); //RF Channel 2 (default, not really needed)
//SPI_WRITE_REG(WRITE_REG+RF_SETUP, 0x03); //Air data rate 1Mbit, -12dBm, Setup LNA
//SPI_WRITE_BUF(WRITE_REG+RX_ADDR_P0, (uint8_t*)&TX_ADDRESS, ADDR_WIDTH); //Set receive address to receive aut-ACK, it is equal to TX_ADDR if enbel enhanced shock burst
//SPI_WRITE_BUF(WRITE_REG+TX_ADDR, (uint8_t*)&TX_ADDRESS, ADDR_WIDTH); //Set transmit address: 0xE7E7E7E7E7
SPI_WRITE_REG(WRITE_REG+RX_PW_P0, 0x04); // 4 byte receive payload
//the next 2 commands are relative with dynamic payload lenght, you need disable them if use static payload length
//enable dynamic payload length, enable dynamic ACK in specific package(then you can
//use command W_TX_PAYLOAD_NOACK to set a specfic package that needn't wait for ACK)
SPI_WRITE_REG(WRITE_REG+DYNPD, 0x01); //as PTX, at least enable pipe 0
SPI_WRITE_REG(WRITE_REG+FEATURE, 0x05);
//SPI_WRITE_REG(WRITE_REG, 0x0E); //power upr
}
else //rx mode
{
SPI_WRITE_REG(WRITE_REG, 0x0D); //RX_DR, TX_DS, MAX_RT interrupts enabled, CRC enabled, CRC encoding with 2bytes and as PRX
//SPI_WRITE_REG(WRITE_REG+EN_AA, 0x3F); //Enable auto-acknowledge for all data pipes(0-5)
SPI_WRITE_REG(WRITE_REG+EN_RXADDR, 0x3F); //Enable RX address for all data pipes(0-5)
//SPI_WRITE_REG(WRITE_REG+SETUP_AW, 0x03); //Setup of address width, reset value is 0x33--5 bytes
SPI_WRITE_REG(WRITE_REG+SETUP_RETR, 0xFF); //Set auto-retransmision, ARD(auto retransmit delay): 1111, ARC(auto retransmit count): 1111
//SPI_WRITE_REG(WRITE_REG+RF_CH, 0x02); //RF Channel 2 (default, not really needed)
//SPI_WRITE_REG(WRITE_REG+RF_SETUP, 0x03); //Air data rate 1Mbit, -12dBm, Setup LNA
//SPI_WRITE_BUF(WRITE_REG+RX_ADDR_P0, (uint8_t*)&TX_ADDRESS, ADDR_WIDTH); //Set receive address for pipe0
//SPI_WRITE_BUF(WRITE_REG+RX_ADDR_P1, (uint8_t*)&RX_ADDRESS, ADDR_WIDTH); //Set receive address for pipe1
//SPI_WRITE_REG(WRITE_REG+RX_ADDR_P2, 0XC3); //Set receive address for pipe2
//SPI_WRITE_REG(WRITE_REG+RX_ADDR_P3, 0XC4); //Set receive address for pipe3
//SPI_WRITE_REG(WRITE_REG+RX_ADDR_P4, 0XC5); //Set receive address for pipe4
//SPI_WRITE_REG(WRITE_REG+RX_ADDR_P5, 0XC6); //Set receive address for pipe5
SPI_WRITE_REG(WRITE_REG+RX_PW_P0, 0x04); // 4 byte receive payload for pipe 0
SPI_WRITE_REG(WRITE_REG+RX_PW_P1, 0x04); // 4 byte receive payload
SPI_WRITE_REG(WRITE_REG+RX_PW_P2, 0x04); // 4 byte receive payload
SPI_WRITE_REG(WRITE_REG+RX_PW_P3, 0x04); // 4 byte receive payload
SPI_WRITE_REG(WRITE_REG+RX_PW_P4, 0x04); // 4 byte receive payload
SPI_WRITE_REG(WRITE_REG+RX_PW_P5, 0x04); // 4 byte receive payload for pipe 5
//don't use static payload length
/*SPI_WRITE_REG(WRITE_REG+RX_PW_P0, 0xFF); //data pipe 0, number of bytes: 32
SPI_WRITE_REG(WRITE_REG+RX_PW_P1, 0xFF); //data pipe 1, number of bytes: 32
SPI_WRITE_REG(WRITE_REG+RX_PW_P2, 0xFF); //data pipe 2, number of bytes: 32
SPI_WRITE_REG(WRITE_REG+RX_PW_P3, 0xFF); //data pipe 3, number of bytes: 32
SPI_WRITE_REG(WRITE_REG+RX_PW_P4, 0xFF); //data pipe 4, number of bytes: 32
SPI_WRITE_REG(WRITE_REG+RX_PW_P5, 0xFF); //data pipe 5, number of bytes: 32
*/
SPI_WRITE_REG(WRITE_REG+DYNPD, 0x3F); //as PRX, enable all pipes
SPI_WRITE_REG(WRITE_REG+FEATURE, 0x05); //enable dynamic payload length
//SPI_WRITE_REG(WRITE_REG, 0x0F); //power upr
}
SPI_CHIP_DISABLE();
/* Start the packet receive process */
process_start(&nrf24l01_process, NULL);
}
/*---------------------------------------------------------------------------*/
int
rf230_get_channel(void)
{
return hal_subregister_read(SR_CHANNEL);
// return channel;
}
/** \brief This function return the Radio Transceivers current state.
*
* \retval P_ON When the external supply voltage (VDD) is
* first supplied to the transceiver IC, the
* system is in the P_ON (Poweron) mode.
* \retval BUSY_RX The radio transceiver is busy receiving a
* frame.
* \retval BUSY_TX The radio transceiver is busy transmitting a
* frame.
* \retval RX_ON The RX_ON mode enables the analog and digital
* receiver blocks and the PLL frequency
* synthesizer.
* \retval TRX_OFF In this mode, the SPI module and crystal
* oscillator are active.
* \retval PLL_ON Entering the PLL_ON mode from TRX_OFF will
* first enable the analog voltage regulator. The
* transceiver is ready to transmit a frame.
* \retval BUSY_RX_AACK The radio was in RX_AACK_ON mode and received
* the Start of Frame Delimiter (SFD). State
* transition to BUSY_RX_AACK is done if the SFD
* is valid.
* \retval BUSY_TX_ARET The radio transceiver is busy handling the
* auto retry mechanism.
* \retval RX_AACK_ON The auto acknowledge mode of the radio is
* enabled and it is waiting for an incomming
* frame.
* \retval TX_ARET_ON The auto retry mechanism is enabled and the
* radio transceiver is waiting for the user to
* send the TX_START command.
* \retval RX_ON_NOCLK The radio transceiver is listening for
* incomming frames, but the CLKM is disabled so
* that the controller could be sleeping.
* However, this is only true if the controller
* is run from the clock output of the radio.
* \retval RX_AACK_ON_NOCLK Same as the RX_ON_NOCLK state, but with the
* auto acknowledge module turned on.
* \retval BUSY_RX_AACK_NOCLK Same as BUSY_RX_AACK, but the controller
* could be sleeping since the CLKM pin is
* disabled.
* \retval STATE_TRANSITION The radio transceiver's state machine is in
* transition between two states.
*/
uint8_t
radio_get_trx_state(void)
{
return hal_subregister_read(SR_TRX_STATUS);
}
