static inline void reset_system(void) { hard_reset(); while (1) { hlt(); } }
/* Check for recovery mode and ensure EC is in RO */ void google_chromeec_early_init(void) { struct chromeec_command cec_cmd; struct ec_response_get_version cec_resp = {{0}}; cec_cmd.cmd_code = EC_CMD_GET_VERSION; cec_cmd.cmd_version = 0; cec_cmd.cmd_data_out = &cec_resp; cec_cmd.cmd_size_in = 0; cec_cmd.cmd_size_out = sizeof(cec_resp); google_chromeec_command(&cec_cmd); if (cec_cmd.cmd_code || (recovery_mode_enabled() && (cec_resp.current_image != EC_IMAGE_RO))) { struct ec_params_reboot_ec reboot_ec; /* Reboot the EC and make it come back in RO mode */ reboot_ec.cmd = EC_REBOOT_COLD; reboot_ec.flags = 0; cec_cmd.cmd_code = EC_CMD_REBOOT_EC; cec_cmd.cmd_version = 0; cec_cmd.cmd_data_in = &reboot_ec; cec_cmd.cmd_size_in = sizeof(reboot_ec); cec_cmd.cmd_size_out = 0; /* ignore response, if any */ printk(BIOS_DEBUG, "Rebooting with EC in RO mode:\n"); google_chromeec_command(&cec_cmd); udelay(1000); hard_reset(); hlt(); } }
void google_chromeec_check_ec_image(int expected_type) { struct chromeec_command cec_cmd; struct ec_response_get_version cec_resp = { { 0 } }; cec_cmd.cmd_code = EC_CMD_GET_VERSION; cec_cmd.cmd_version = 0; cec_cmd.cmd_data_out = &cec_resp; cec_cmd.cmd_size_in = 0; cec_cmd.cmd_size_out = sizeof(cec_resp); cec_cmd.cmd_dev_index = 0; google_chromeec_command(&cec_cmd); if (cec_cmd.cmd_code || cec_resp.current_image != expected_type) { struct ec_params_reboot_ec reboot_ec; /* Reboot the EC and make it come back in RO mode */ reboot_ec.cmd = EC_REBOOT_COLD; reboot_ec.flags = 0; cec_cmd.cmd_code = EC_CMD_REBOOT_EC; cec_cmd.cmd_version = 0; cec_cmd.cmd_data_in = &reboot_ec; cec_cmd.cmd_size_in = sizeof(reboot_ec); cec_cmd.cmd_size_out = 0; /* ignore response, if any */ cec_cmd.cmd_dev_index = 0; printk(BIOS_DEBUG, "Rebooting with EC in RO mode:\n"); post_code(0); /* clear current post code */ google_chromeec_command(&cec_cmd); udelay(1000); hard_reset(); halt(); } }
void main(unsigned long bist) { if (bist == 0) { if (memory_initialized()) hard_reset(); } /* Set southbridge and superio gpios */ mb_gpio_init(); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure. */ report_bist_failure(bist); /* disable TCO timers */ i82801dx_halt_tco_timer(); /* Setup mainboard specific registers */ mb_early_setup(); /* Initialize memory */ sdram_initialize(); }
static void ramstage_cache_invalid(void) { printk(BIOS_ERR, "ramstage cache invalid.\n"); if (IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE)) { hard_reset(); halt(); } }
void vboot_reboot(void) { if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART)) cbmem_dump_console(); vboot_platform_prepare_reboot(); hard_reset(); die("failed to reboot"); }
// XXX refactor this out of this driver void PWMIN::_freeze_test() { /* reset if last poll time was way back and a read was recently requested */ if (hrt_elapsed_time(&_last_poll_time) > TIMEOUT_POLL && hrt_elapsed_time(&_last_read_time) < TIMEOUT_READ) { hard_reset(); } }
/* The FSP returns here after the fsp_early_init call */ void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; if (Status == 0xFFFFFFFF) { hard_reset(); } romstage_main_continue(Status, HobListPtr); }
int sys_reboot( void ) { thread_id hThread; int i; write_kernel_config(); // Since we (hopefully) wont be killed by the signal we must close our files manually. for ( i = 0; i < 256; ++i ) { sys_close( i ); } printk( "Send TERM signals\n" ); for ( hThread = get_prev_thread( -1 ); -1 != hThread; hThread = get_prev_thread( hThread ) ) { if ( hThread > 1 ) { sys_kill( hThread, SIGTERM ); } } snooze( 2000000 ); printk( "Send KILL signals\n" ); for ( hThread = get_prev_thread( -1 ); -1 != hThread; hThread = get_prev_thread( hThread ) ) { if ( hThread > 1 ) { sys_kill( hThread, SIGKILL ); } } snooze( 1000000 ); printk( "Flush block cache()\n" ); flush_block_cache(); printk( "Shut down VFS\n" ); shutdown_vfs(); printk( "shut down block cache()\n" ); shutdown_block_cache(); shutdown_ap_processors(); printk( "Rebooting Pyro...\n" ); // Just to be sure :) snooze( 1000000 ); hard_reset(); printk( "It must be a sign!\n" ); return ( 0 ); }
static void init_vboot(int bootmode) { u32 result; u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; #ifdef UBOOT_DOES_TPM_STARTUP /* Doing TPM startup when we're not coming in on the S3 resume path * saves us roughly 20ms in boot time only. This does not seem to * be worth an API change to vboot_reference-firmware right now, so * let's keep the code around, but just bail out early: */ if (bootmode != 2) return; #endif printk(BIOS_DEBUG, "Verified boot TPM initialization.\n"); printk(BIOS_SPEW, "TPM: Init\n"); if (tis_init()) return; printk(BIOS_SPEW, "TPM: Open\n"); if (tis_open()) return; if (bootmode == 2) { /* S3 Resume */ printk(BIOS_SPEW, "TPM: Resume\n"); result = TlclSendReceive(tpm_resume_cmd.buffer, response, sizeof(response)); if (result == TPM_E_INVALID_POSTINIT) { /* We're on a platform where the TPM maintains power * in S3, so it's already initialized. */ printk(BIOS_DEBUG, "TPM: Already initialized.\n"); return; } } else { printk(BIOS_SPEW, "TPM: Startup\n"); result = TlclSendReceive(tpm_startup_cmd.buffer, response, sizeof(response)); } if (result == TPM_SUCCESS) { printk(BIOS_SPEW, "TPM: OK.\n"); return; } #if !MOCK_TPM printk(BIOS_ERR, "TPM: Error code 0x%x. Hard reset!\n", result); hard_reset(); #endif }
static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay) { if (i2c_writeb(bus, AS3722_I2C_ADDR, reg, val)) { printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n", __func__, reg, val); /* Reset the SoC on any PMIC write error */ hard_reset(); } else { if (do_delay) udelay(500); } }
void google_chromeec_init(void) { struct chromeec_command cec_cmd; struct ec_response_get_version cec_resp = {{0}}; printk(BIOS_DEBUG, "Google Chrome EC: Initializing keyboard.\n"); google_chromeec_hello(); cec_cmd.cmd_code = EC_CMD_GET_VERSION; cec_cmd.cmd_version = 0; cec_cmd.cmd_data_out = &cec_resp; cec_cmd.cmd_size_in = 0; cec_cmd.cmd_size_out = sizeof(cec_resp); cec_cmd.cmd_dev_index = 0; google_chromeec_command(&cec_cmd); if (cec_cmd.cmd_code) { printk(BIOS_DEBUG, "Google Chrome EC: version command failed!\n"); } else { printk(BIOS_DEBUG, "Google Chrome EC: version:\n"); printk(BIOS_DEBUG, " ro: %s\n", cec_resp.version_string_ro); printk(BIOS_DEBUG, " rw: %s\n", cec_resp.version_string_rw); printk(BIOS_DEBUG, " running image: %d\n", cec_resp.current_image); ec_image_type = cec_resp.current_image; } if (cec_cmd.cmd_code || (recovery_mode_enabled() && (cec_resp.current_image != EC_IMAGE_RO))) { struct ec_params_reboot_ec reboot_ec; /* Reboot the EC and make it come back in RO mode */ reboot_ec.cmd = EC_REBOOT_COLD; reboot_ec.flags = 0; cec_cmd.cmd_code = EC_CMD_REBOOT_EC; cec_cmd.cmd_version = 0; cec_cmd.cmd_data_in = &reboot_ec; cec_cmd.cmd_size_in = sizeof(reboot_ec); cec_cmd.cmd_size_out = 0; /* ignore response, if any */ cec_cmd.cmd_dev_index = 0; printk(BIOS_DEBUG, "Rebooting with EC in RO mode:\n"); post_code(0); /* clear current post code */ google_chromeec_command(&cec_cmd); udelay(1000); hard_reset(); halt(); } }
static void __attribute__((noinline)) romstage(void) { timestamp_init(0); timestamp_add_now(TS_START_ROMSTAGE); console_init(); exception_init(); sdram_init(get_sdram_config()); /* used for MMU and CBMEM setup, in MB */ u32 dram_start_mb = (uintptr_t)_dram/MiB; u32 dram_end_mb = sdram_max_addressable_mb(); u32 dram_size_mb = dram_end_mb - dram_start_mb; configure_l2_cache(); mmu_init(); /* Device memory below DRAM is uncached. */ mmu_config_range(0, dram_start_mb, DCACHE_OFF); /* SRAM is cached. MMU code will round size up to page size. */ mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB), DCACHE_WRITEBACK); /* DRAM is cached. */ mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK); /* A window for DMA is uncached. */ mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); /* The space above DRAM is uncached. */ if (dram_end_mb < 4096) mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF); mmu_disable_range(0, 1); dcache_mmu_enable(); /* * A watchdog reset only resets part of the system so it ends up in * a funny state. If that happens, we need to reset the whole machine. */ if (power_reset_status() == POWER_RESET_WATCHDOG) { printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n"); hard_reset(); } /* FIXME: this may require coordination with moving timestamps */ cbmem_initialize_empty(); early_mainboard_init(); run_ramstage(); }
bool load( const char *ptr, size_t len ) { if( !(ptr && len) ) { return false; } // clear and add first dummy/invalid animation *this = controller(); hard_reset(); // parse animation format (see top of file) wire::strings lines = wire::string( ptr, len ).tokenize("\f\b\v\r\n"); for( auto &line : lines ) { wire::strings words = line.tokenize("()[]:-~;:\t "); if( words.size() < 4 ) continue; wire::string label = words.front(); if( label != "frame" && label.as<int>() > 0 ) label = "frame"; else words.pop_front(); wire::string begin = words.front(); words.pop_front(); while( begin.size() && begin.front() == '0' ) begin.pop_front(); wire::string end = words.front(); words.pop_front(); while( end.size() && end.front() == '0' ) end.pop_front(); wire::string name = words.str("\1 "); while( name.size() && name.back() == ' ' ) name.pop_back(); name = name.replace(" ", "-").lowercase(); bool loopable = (name.find("-loop") != std::string::npos); // insert animation anim; anim.id = animations.size(); anim.name = name; anim.loopable = loopable; anim.begin = begin.as<unsigned>(); anim.end = end.as<unsigned>(); if( label != "frame" ) continue; if( anim.end < anim.begin ) continue; ids[ anim.id ] = anim.name; names[ anim.name ] = anim.id; animations.push_back( anim ); } ids[ 0 ] = ""; names[ "" ] = 0; animations[0] = animation(); return true; }
static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) { u16 val; u16 ctl; int flag = 0; do { val = pci_read_config16(dev, 0x76); printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val); if ((val & (1<<11)) && (!flag)) { /* training error */ ctl = pci_read_config16(dev, 0x74); pci_write_config16(dev, 0x74, (ctl | (1<<5))); val = pci_read_config16(dev, 0x76); printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val); flag=1; hard_reset(); } } while (val & (3<<10)); return pciexp_scan_bridge(dev, max); }
/* * handle ioctl requests */ int PWMIN::ioctl(struct file *filp, int cmd, unsigned long arg) { switch (cmd) { case SENSORIOCSQUEUEDEPTH: { /* lower bound is mandatory, upper bound is a sanity check */ if ((arg < 1) || (arg > 500)) { return -EINVAL; } irqstate_t flags = px4_enter_critical_section(); if (!_reports->resize(arg)) { px4_leave_critical_section(flags); return -ENOMEM; } px4_leave_critical_section(flags); return OK; } case SENSORIOCGQUEUEDEPTH: return _reports->size(); case SENSORIOCRESET: /* user has asked for the timer to be reset. This may * be needed if the pin was used for a different * purpose (such as PWM output) */ _timer_init(); /* also reset the sensor */ hard_reset(); return OK; default: /* give it to the superclass */ return CDev::ioctl(filp, cmd, arg); } }
int w5200_init(void) { count = 0; sock = 0; fst = &qd[0]; lst = &qd[0]; // Turn everything on W5200_PWR_ON; W5200_CS_STOP; W5200_RST_STOP; // Give it some time delay_millis(200); // Go hard in the paint hard_reset(); uint8_t vsr = read_VRSN(); while(vsr != 0x03) { vsr = read_VRSN(); delay_for_1000_nops_x(8); } write_MR(MR_CONF); write_GAR(gateway_ip); write_SUBR(w52_const_subnet_classC); write_SHAR(w52_const_mac_default); write_SIPR(dest_ip); write_IMR(IMR_CONF); write_IMR(IMR2_CONF); write_IR2(IR2_CONF); write_PHYST(PHY_CONF); return init_sockets(); }
void raminit(struct romstage_params *params) { const EFI_GUID bootldr_tolum_guid = FSP_BOOTLOADER_TOLUM_HOB_GUID; EFI_HOB_RESOURCE_DESCRIPTOR *cbmem_root; FSP_INFO_HEADER *fsp_header; EFI_HOB_RESOURCE_DESCRIPTOR *fsp_memory; FSP_MEMORY_INIT fsp_memory_init; FSP_MEMORY_INIT_PARAMS fsp_memory_init_params; const EFI_GUID fsp_reserved_guid = FSP_RESERVED_MEMORY_RESOURCE_HOB_GUID; void *fsp_reserved_memory_area; FSP_INIT_RT_COMMON_BUFFER fsp_rt_common_buffer; void *hob_list_ptr; FSP_SMBIOS_MEMORY_INFO *memory_info_hob; const EFI_GUID memory_info_hob_guid = FSP_SMBIOS_MEMORY_INFO_GUID; MEMORY_INIT_UPD memory_init_params; const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; u32 *mrc_hob; u32 fsp_reserved_bytes; MEMORY_INIT_UPD *original_params; struct pei_data *pei_ptr; EFI_STATUS status; VPD_DATA_REGION *vpd_ptr; UPD_DATA_REGION *upd_ptr; int fsp_verification_failure = 0; #if IS_ENABLED(CONFIG_DISPLAY_HOBS) unsigned long int data; EFI_PEI_HOB_POINTERS hob_ptr; #endif /* * Find and copy the UPD region to the stack so the platform can modify * the settings if needed. Modifications to the UPD buffer are done in * the platform callback code. The platform callback code is also * responsible for assigning the UpdDataRngPtr to this buffer if any * updates are made. The default state is to leave the UpdDataRngPtr * set to NULL. This indicates that the FSP code will use the UPD * region in the FSP binary. */ post_code(0x34); fsp_header = params->chipset_context; vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset + fsp_header->ImageBase); printk(BIOS_DEBUG, "VPD Data: 0x%p\n", vpd_ptr); upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset + fsp_header->ImageBase); printk(BIOS_DEBUG, "UPD Data: 0x%p\n", upd_ptr); original_params = (void *)((u8 *)upd_ptr + upd_ptr->MemoryInitUpdOffset); memcpy(&memory_init_params, original_params, sizeof(memory_init_params)); /* Zero fill RT Buffer data and start populating fields. */ memset(&fsp_rt_common_buffer, 0, sizeof(fsp_rt_common_buffer)); pei_ptr = params->pei_data; if (pei_ptr->boot_mode == SLEEP_STATE_S3) { fsp_rt_common_buffer.BootMode = BOOT_ON_S3_RESUME; } else if (pei_ptr->saved_data != NULL) { fsp_rt_common_buffer.BootMode = BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; } else { fsp_rt_common_buffer.BootMode = BOOT_WITH_FULL_CONFIGURATION; } fsp_rt_common_buffer.UpdDataRgnPtr = &memory_init_params; fsp_rt_common_buffer.BootLoaderTolumSize = cbmem_overhead_size(); /* Get any board specific changes */ fsp_memory_init_params.NvsBufferPtr = (void *)pei_ptr->saved_data; fsp_memory_init_params.RtBufferPtr = &fsp_rt_common_buffer; fsp_memory_init_params.HobListPtr = &hob_list_ptr; /* Update the UPD data */ soc_memory_init_params(params, &memory_init_params); mainboard_memory_init_params(params, &memory_init_params); if (IS_ENABLED(CONFIG_MMA)) setup_mma(&memory_init_params); post_code(0x36); /* Display the UPD data */ if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA)) soc_display_memory_init_params(original_params, &memory_init_params); /* Call FspMemoryInit to initialize RAM */ fsp_memory_init = (FSP_MEMORY_INIT)(fsp_header->ImageBase + fsp_header->FspMemoryInitEntryOffset); printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_memory_init); printk(BIOS_SPEW, " 0x%p: NvsBufferPtr\n", fsp_memory_init_params.NvsBufferPtr); printk(BIOS_SPEW, " 0x%p: RtBufferPtr\n", fsp_memory_init_params.RtBufferPtr); printk(BIOS_SPEW, " 0x%p: HobListPtr\n", fsp_memory_init_params.HobListPtr); timestamp_add_now(TS_FSP_MEMORY_INIT_START); post_code(POST_FSP_MEMORY_INIT); status = fsp_memory_init(&fsp_memory_init_params); post_code(0x37); timestamp_add_now(TS_FSP_MEMORY_INIT_END); printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); if (status != EFI_SUCCESS) die("ERROR - FspMemoryInit failed to initialize memory!\n"); /* Locate the FSP reserved memory area */ fsp_reserved_bytes = 0; fsp_memory = get_next_resource_hob(&fsp_reserved_guid, hob_list_ptr); if (fsp_memory == NULL) { fsp_verification_failure = 1; printk(BIOS_DEBUG, "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n"); } else { fsp_reserved_bytes = fsp_memory->ResourceLength; printk(BIOS_DEBUG, "Reserving 0x%016lx bytes for FSP\n", (unsigned long int)fsp_reserved_bytes); } /* Display SMM area */ #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) char *smm_base; size_t smm_size; smm_region((void **)&smm_base, &smm_size); printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size); printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base); #endif /* Migrate CAR data */ printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top()); if (pei_ptr->boot_mode != SLEEP_STATE_S3) { cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, fsp_reserved_bytes); } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, fsp_reserved_bytes)) { #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ hard_reset(); #endif } /* Save the FSP runtime parameters. */ fsp_set_runtime(fsp_header, hob_list_ptr); /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */ cbmem_root = get_next_resource_hob(&bootldr_tolum_guid, hob_list_ptr); if (cbmem_root == NULL) { fsp_verification_failure = 1; printk(BIOS_ERR, "7.4: FSP_BOOTLOADER_TOLUM_HOB missing!\n"); printk(BIOS_ERR, "BootLoaderTolumSize: 0x%08x bytes\n", fsp_rt_common_buffer.BootLoaderTolumSize); } /* Locate the FSP_SMBIOS_MEMORY_INFO HOB */ memory_info_hob = get_next_guid_hob(&memory_info_hob_guid, hob_list_ptr); if (NULL == memory_info_hob) { printk(BIOS_ERR, "FSP_SMBIOS_MEMORY_INFO HOB missing!\n"); fsp_verification_failure = 1; } else { printk(BIOS_DEBUG, "FSP_SMBIOS_MEMORY_INFO HOB: 0x%p\n", memory_info_hob); } #if IS_ENABLED(CONFIG_DISPLAY_HOBS) if (hob_list_ptr == NULL) die("ERROR - HOB pointer is NULL!\n"); /* * Verify that FSP is generating the required HOBs: * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0 * 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified above * 7.3: FSP_NON_VOLATILE_STORAGE_HOB verified below * 7.4: FSP_BOOTLOADER_TOLUM_HOB verified above * 7.5: EFI_PEI_GRAPHICS_INFO_HOB produced by SiliconInit * FSP_SMBIOS_MEMORY_INFO HOB verified above */ if (NULL != cbmem_root) { printk(BIOS_DEBUG, "7.4: FSP_BOOTLOADER_TOLUM_HOB: 0x%p\n", cbmem_root); data = cbmem_root->PhysicalStart; printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data); data = cbmem_root->ResourceLength; printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data); } hob_ptr.Raw = get_next_guid_hob(&mrc_guid, hob_list_ptr); if (NULL == hob_ptr.Raw) { printk(BIOS_ERR, "7.3: FSP_NON_VOLATILE_STORAGE_HOB missing!\n"); fsp_verification_failure = (params->pei_data->saved_data == NULL) ? 1 : 0; } else { printk(BIOS_DEBUG, "7.3: FSP_NON_VOLATILE_STORAGE_HOB: 0x%p\n", hob_ptr.Raw); } if (fsp_memory != NULL) { printk(BIOS_DEBUG, "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB: 0x%p\n", fsp_memory); data = fsp_memory->PhysicalStart; printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data); data = fsp_memory->ResourceLength; printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data); } /* Verify all the HOBs are present */ if (fsp_verification_failure) printk(BIOS_DEBUG, "ERROR - Missing one or more required FSP HOBs!\n"); /* Display the HOBs */ print_hob_type_structure(0, hob_list_ptr); #endif /* Get the address of the CBMEM region for the FSP reserved memory */ fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY); printk(BIOS_DEBUG, "0x%p: fsp_reserved_memory_area\n", fsp_reserved_memory_area); /* Verify the order of CBMEM root and FSP memory */ if ((fsp_memory != NULL) && (cbmem_root != NULL) && (cbmem_root->PhysicalStart <= fsp_memory->PhysicalStart)) { fsp_verification_failure = 1; printk(BIOS_DEBUG, "ERROR - FSP reserved memory above CBMEM root!\n"); } /* Verify that the FSP memory was properly reserved */ if ((fsp_memory != NULL) && ((fsp_reserved_memory_area == NULL) || (fsp_memory->PhysicalStart != (unsigned int)fsp_reserved_memory_area))) { fsp_verification_failure = 1; printk(BIOS_DEBUG, "ERROR - Reserving FSP memory area!\n"); #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) if (cbmem_root != NULL) { size_t delta_bytes = (unsigned int)smm_base - cbmem_root->PhysicalStart - cbmem_root->ResourceLength; printk(BIOS_DEBUG, "0x%08x: Chipset reserved bytes reported by FSP\n", (unsigned int)delta_bytes); die("Please verify the chipset reserved size\n"); } #endif } /* Verify the FSP 1.1 HOB interface */ if (fsp_verification_failure) die("ERROR - Coreboot's requirements not met by FSP binary!\n"); /* Display the memory configuration */ report_memory_config(); /* Locate the memory configuration data to speed up the next reboot */ mrc_hob = get_next_guid_hob(&mrc_guid, hob_list_ptr); if (mrc_hob == NULL) printk(BIOS_DEBUG, "Memory Configuration Data Hob not present\n"); else { pei_ptr->data_to_save = GET_GUID_HOB_DATA(mrc_hob); pei_ptr->data_to_save_size = ALIGN( ((u32)GET_HOB_LENGTH(mrc_hob)), 16); } }
static void root_dev_reset(struct bus *bus) { printk(BIOS_INFO, "Resetting board...\n"); hard_reset(); }
void reset_system(void) { hard_reset(); halt(); }
void reboot_from_watchdog(void) { printk(BIOS_INFO, "Last reset was watchdog, reboot again to reset TPM!\n"); write32(_watchdog_tombstone, WATCHDOG_TOMBSTONE_MAGIC); hard_reset(); }
static void fatal_error(void) { printk(BIOS_ERR, "vboot encountered fatal error. Resetting.\n"); hard_reset(); }
void hardwaremain(int boot_complete) { struct lb_memory *lb_mem; void *payload; timestamp_stash(TS_START_RAMSTAGE); post_code(POST_ENTRY_RAMSTAGE); #if CONFIG_COVERAGE coverage_init(); #endif /* console_init() MUST PRECEDE ALL printk()! */ console_init(); post_code(POST_CONSOLE_READY); printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n", coreboot_version, coreboot_extra_version, coreboot_build, (boot_complete)?"rebooting":"booting"); post_code(POST_CONSOLE_BOOT_MSG); /* If we have already booted attempt a hard reboot */ if (boot_complete) { hard_reset(); } /* FIXME: Is there a better way to handle this? */ init_timer(); timestamp_stash(TS_DEVICE_ENUMERATE); /* Initialize chips early, they might disable unused devices. */ dev_initialize_chips(); /* Find the devices we don't have hard coded knowledge about. */ dev_enumerate(); post_code(POST_DEVICE_ENUMERATION_COMPLETE); timestamp_stash(TS_DEVICE_CONFIGURE); /* Now compute and assign the bus resources. */ dev_configure(); post_code(POST_DEVICE_CONFIGURATION_COMPLETE); timestamp_stash(TS_DEVICE_ENABLE); /* Now actually enable devices on the bus */ dev_enable(); post_code(POST_DEVICES_ENABLED); timestamp_stash(TS_DEVICE_INITIALIZE); /* And of course initialize devices on the bus */ dev_initialize(); post_code(POST_DEVICES_INITIALIZED); timestamp_stash(TS_DEVICE_DONE); cbmem_initialize(); #if CONFIG_CONSOLE_CBMEM cbmemc_reinit(); #endif timestamp_sync(); #if CONFIG_HAVE_ACPI_RESUME suspend_resume(); post_code(0x8a); #endif timestamp_add_now(TS_CBMEM_POST); if (cbmem_post_handling) cbmem_post_handling(); timestamp_add_now(TS_WRITE_TABLES); /* Now that we have collected all of our information * write our configuration tables. */ lb_mem = write_tables(); timestamp_add_now(TS_LOAD_PAYLOAD); payload = cbfs_load_payload(CBFS_DEFAULT_MEDIA, CONFIG_CBFS_PREFIX "/payload"); if (! payload) die("Could not find a payload\n"); selfboot(lb_mem, payload); printk(BIOS_EMERG, "Boot failed"); }
void ramstage_cache_invalid(void) { if (IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE)) /* Perform cold reset on invalid ramstage cache. */ hard_reset(); }
void reboot_from_watchdog(void) { printk(BIOS_INFO, "Last reset was watchdog, reboot again to reset TPM!\n"); mark_watchdog_tombstone(); hard_reset(); }
/* Entry from the mainboard. */ void romstage_common(struct romstage_params *params) { const struct mrc_saved_data *cache; struct romstage_handoff *handoff; struct pei_data *pei_data; post_code(0x32); timestamp_add_now(TS_BEFORE_INITRAM); pei_data = params->pei_data; pei_data->boot_mode = params->power_state->prev_sleep_state; #if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) if (params->power_state->prev_sleep_state != ACPI_S3) boot_count_increment(); #endif /* Perform remaining SOC initialization */ soc_pre_ram_init(params); post_code(0x33); /* Check recovery and MRC cache */ params->pei_data->saved_data_size = 0; params->pei_data->saved_data = NULL; if (!params->pei_data->disable_saved_data) { if (vboot_recovery_mode_enabled()) { /* Recovery mode does not use MRC cache */ printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); } else if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) && (!mrc_cache_get_current_with_version(&cache, params->fsp_version))) { /* MRC cache found */ params->pei_data->saved_data_size = cache->size; params->pei_data->saved_data = &cache->data[0]; } else if (params->pei_data->boot_mode == ACPI_S3) { /* Waking from S3 and no cache. */ printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); post_code(POST_RESUME_FAILURE); hard_reset(); } else { printk(BIOS_DEBUG, "No MRC cache found.\n"); mainboard_check_ec_image(params); } } /* Initialize RAM */ raminit(params); timestamp_add_now(TS_AFTER_INITRAM); /* Save MRC output */ if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) { printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save, pei_data->data_to_save_size); if ((params->pei_data->boot_mode != ACPI_S3) && (params->pei_data->data_to_save_size != 0) && (params->pei_data->data_to_save != NULL)) mrc_cache_stash_data_with_version( params->pei_data->data_to_save, params->pei_data->data_to_save_size, params->fsp_version); } /* Save DIMM information */ mainboard_save_dimm_info(params); /* Create romstage handof information */ handoff = romstage_handoff_find_or_add(); if (handoff != NULL) handoff->s3_resume = (params->power_state->prev_sleep_state == ACPI_S3); else { printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); hard_reset(); } /* * Initialize the TPM, unless the TPM was already initialized * in verstage and used to verify romstage. */ if (IS_ENABLED(CONFIG_LPC_TPM) && !IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) init_tpm(params->power_state->prev_sleep_state == ACPI_S3); }
void global_reset(void) { global_reset_enable(1); hard_reset(); }
static inline void reset_system(void) { hard_reset(); halt(); }
void init_tpm(int s3resume) { u32 result; u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; if (CONFIG_TPM_DEACTIVATE) { printk(BIOS_SPEW, "TPM: Deactivate\n"); result = TlclSendReceive(tpm_deactivate_cmd.buffer, response, sizeof(response)); if (result == TPM_SUCCESS) { printk(BIOS_SPEW, "TPM: OK.\n"); return; } printk(BIOS_ERR, "TPM: Error code 0x%x.\n", result); return; } /* Doing TPM startup when we're not coming in on the S3 resume path * saves us roughly 20ms in boot time only. This does not seem to * be worth an API change to vboot_reference-firmware right now, so * let's keep the code around, but just bail out early: */ if (s3resume ? CONFIG_NO_TPM_RESUME : CONFIG_SKIP_TPM_STARTUP_ON_NORMAL_BOOT) return; printk(BIOS_DEBUG, "TPM initialization.\n"); printk(BIOS_SPEW, "TPM: Init\n"); if (tis_init()) return; printk(BIOS_SPEW, "TPM: Open\n"); if (tis_open()) return; if (s3resume) { /* S3 Resume */ printk(BIOS_SPEW, "TPM: Resume\n"); result = TlclSendReceive(tpm_resume_cmd.buffer, response, sizeof(response)); if (result == TPM_E_INVALID_POSTINIT) { /* We're on a platform where the TPM maintains power * in S3, so it's already initialized. */ printk(BIOS_DEBUG, "TPM: Already initialized.\n"); return; } } else { printk(BIOS_SPEW, "TPM: Startup\n"); result = TlclSendReceive(tpm_startup_cmd.buffer, response, sizeof(response)); } if (result == TPM_SUCCESS) { printk(BIOS_SPEW, "TPM: OK.\n"); return; } printk(BIOS_ERR, "TPM: Error code 0x%x.\n", result); if (CONFIG_TPM_INIT_FAILURE_IS_FATAL) { printk(BIOS_ERR, "Hard reset!\n"); post_code(POST_TPM_FAILURE); if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART)) cbmem_dump_console(); hard_reset(); } }
asmlinkage void car_stage_entry(void) { void *hob_list_ptr; const void *mrc_data; struct range_entry fsp_mem, reg_car; struct postcar_frame pcf; size_t mrc_data_size; uintptr_t top_of_ram; int prev_sleep_state; struct romstage_handoff *handoff; struct chipset_power_state *ps = car_get_var_ptr(&power_state); timestamp_add_now(TS_START_ROMSTAGE); soc_early_romstage_init(); disable_watchdog(); console_init(); prev_sleep_state = fill_power_state(ps); /* Make sure the blob does not override our data in CAR */ range_entry_init(®_car, (uintptr_t)_car_relocatable_data_end, (uintptr_t)_car_region_end, 0); if (fsp_memory_init(&hob_list_ptr, ®_car) != FSP_SUCCESS) { die("FSP memory init failed. Giving up."); } fsp_find_reserved_memory(&fsp_mem, hob_list_ptr); /* initialize cbmem by adding FSP reserved memory first thing */ if (prev_sleep_state != SLEEP_STATE_S3) { cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, range_entry_size(&fsp_mem)); } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, range_entry_size(&fsp_mem))) { if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ hard_reset(); } } /* make sure FSP memory is reserved in cbmem */ if (range_entry_base(&fsp_mem) != (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) die("Failed to accommodate FSP reserved memory request"); /* Now that CBMEM is up, save the list so ramstage can use it */ fsp_save_hob_list(hob_list_ptr); /* Save MRC Data to CBMEM */ if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) && (prev_sleep_state != SLEEP_STATE_S3)) { mrc_data = fsp_find_nv_storage_data(&mrc_data_size); if (mrc_data && mrc_cache_stash_data(mrc_data, mrc_data_size) < 0) printk(BIOS_ERR, "Failed to stash MRC data\n"); } /* Create romstage handof information */ handoff = romstage_handoff_find_or_add(); if (handoff != NULL) handoff->s3_resume = (prev_sleep_state == SLEEP_STATE_S3); else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); /* * We need to make sure ramstage will be run cached. At this point exact * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ top_of_ram = (uintptr_t) cbmem_top(); /* cbmem_top() needs to be at least 16 MiB aligned */ assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK); run_postcar_phase(&pcf); }