void h8_sci_device::rx_done() { if(!(ssr & SSR_FER)) { if((smr & SMR_PE) && rx_parity) { ssr |= SSR_PER; logerror("%s: Recieve parity error\n", tag()); } else if(ssr & SSR_RDRF) { ssr |= SSR_ORER; logerror("%s: Recieve overrun\n", tag()); } else { ssr |= SSR_RDRF; logerror("%s: Recieved %02x\n", tag(), rsr); rdr = rsr; } } if(scr & SCR_RIE) { if(has_recv_error()) intc->internal_interrupt(eri_int); else intc->internal_interrupt(rxi_int); } if((scr & SCR_RE) && !has_recv_error() && !is_sync_start()) rx_start(); else { clock_stop(CLK_RX); rx_state = ST_IDLE; } }
void h8_sci_device::rx_done() { if(!(ssr & SSR_FER)) { if((smr & SMR_PE) && rx_parity) { ssr |= SSR_PER; if(V>=1) logerror("Receive parity error\n"); } else if(ssr & SSR_RDRF) { ssr |= SSR_ORER; if(V>=1) logerror("Receive overrun\n"); } else { ssr |= SSR_RDRF; if(V>=1) logerror("Received %02x '%c'\n", rsr, rsr >= 32 && rsr < 127 ? rsr : '.'); rdr = rsr; } } if(scr & SCR_RIE) { if(has_recv_error()) intc->internal_interrupt(eri_int); else intc->internal_interrupt(rxi_int); } if((scr & SCR_RE) && !has_recv_error() && !is_sync_start()) rx_start(); else { clock_stop(CLK_RX); rx_state = ST_IDLE; } }
void h8_sci_device::tx_start() { ssr |= SSR_TDRE; tsr = tdr; tx_parity = smr & SMR_OE ? 0 : 1; logerror("%s: start transmit %02x\n", tag(), tsr); if(scr & SCR_TIE) intc->internal_interrupt(txi_int); if(smr & SMR_CA) { tx_state = ST_BIT; tx_bit = 8; } else { tx_state = ST_START; tx_bit = 1; } clock_start(CLK_TX); if(rx_state == ST_IDLE && !has_recv_error() && is_sync_start()) rx_start(); }