int drm_ht_create(struct drm_open_hash *ht, unsigned int order) { ht->size = 1 << order; ht->order = order; ht->table = NULL; ht->table = hashinit_flags(ht->size, DRM_MEM_HASHTAB, &ht->mask, HASH_NOWAIT); if (!ht->table) { DRM_ERROR("Out of memory for hash table\n"); return -ENOMEM; } return 0; }
/* * Allocate and initialize a hash table with default flag: may sleep. */ void * hashinit(int elements, struct malloc_type *type, u_long *hashmask) { return (hashinit_flags(elements, type, hashmask, HASH_WAITOK)); }
/* * Ground control to Major TOM * Commencing countdown, engines on */ static int t3_tom_activate(struct adapter *sc) { struct tom_data *td; struct toedev *tod; int i, rc = 0; struct mc5_params *mc5 = &sc->params.mc5; u_int ntids, natids, mtus; ADAPTER_LOCK_ASSERT_OWNED(sc); /* for sc->flags */ /* per-adapter softc for TOM */ td = malloc(sizeof(*td), M_CXGB, M_ZERO | M_NOWAIT); if (td == NULL) return (ENOMEM); /* List of TOE PCBs and associated lock */ mtx_init(&td->toep_list_lock, "PCB list lock", NULL, MTX_DEF); TAILQ_INIT(&td->toep_list); /* Listen context */ mtx_init(&td->lctx_hash_lock, "lctx hash lock", NULL, MTX_DEF); td->listen_hash = hashinit_flags(LISTEN_HASH_SIZE, M_CXGB, &td->listen_mask, HASH_NOWAIT); /* TID release task */ TASK_INIT(&td->tid_release_task, 0 , t3_process_tid_release_list, td); mtx_init(&td->tid_release_lock, "tid release", NULL, MTX_DEF); /* L2 table */ td->l2t = t3_init_l2t(L2T_SIZE); if (td->l2t == NULL) { rc = ENOMEM; goto done; } /* TID tables */ ntids = t3_mc5_size(&sc->mc5) - mc5->nroutes - mc5->nfilters - mc5->nservers; natids = min(ntids / 2, 64 * 1024); rc = alloc_tid_tabs(&td->tid_maps, ntids, natids, mc5->nservers, 0x100000 /* ATID_BASE */, ntids); if (rc != 0) goto done; /* CPL handlers */ t3_init_listen_cpl_handlers(sc); t3_init_l2t_cpl_handlers(sc); t3_init_cpl_io(sc); /* toedev ops */ tod = &td->tod; init_toedev(tod); tod->tod_softc = sc; tod->tod_connect = t3_connect; tod->tod_listen_start = t3_listen_start; tod->tod_listen_stop = t3_listen_stop; tod->tod_rcvd = t3_rcvd; tod->tod_output = t3_tod_output; tod->tod_send_rst = t3_send_rst; tod->tod_send_fin = t3_send_fin; tod->tod_pcb_detach = t3_pcb_detach; tod->tod_l2_update = t3_l2_update; tod->tod_syncache_added = t3_syncache_added; tod->tod_syncache_removed = t3_syncache_removed; tod->tod_syncache_respond = t3_syncache_respond; tod->tod_offload_socket = t3_offload_socket; /* port MTUs */ mtus = sc->port[0].ifp->if_mtu; if (sc->params.nports > 1) mtus |= sc->port[1].ifp->if_mtu << 16; t3_write_reg(sc, A_TP_MTU_PORT_TABLE, mtus); t3_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd, sc->params.rev == 0 ? sc->port[0].ifp->if_mtu : 0xffff); /* SMT entry for each port */ for_each_port(sc, i) { write_smt_entry(sc, i); TOEDEV(sc->port[i].ifp) = &td->tod; }
/** * Allocate and initialize a hash table with default flag: may sleep. */ void * hashinit(int elements, unsigned long * hashmask) { return hashinit_flags(elements, hashmask, HASH_WAITOK); }