//--------------------------------------------------------------------+
// CLASS-USBD API (don't require to verify parameters)
//--------------------------------------------------------------------+
bool usbh_init(void)
{
tu_memclr(_usbh_devices, sizeof(usbh_device_t)*(CFG_TUSB_HOST_DEVICE_MAX+1));
//------------- Enumeration & Reporter Task init -------------//
_usbh_q = osal_queue_create( &_usbh_qdef );
TU_ASSERT(_usbh_q != NULL);
//------------- Semaphore, Mutex for Control Pipe -------------//
for(uint8_t i=0; i<CFG_TUSB_HOST_DEVICE_MAX+1; i++) // including address zero
{
usbh_device_t * const dev = &_usbh_devices[i];
dev->control.sem_hdl = osal_semaphore_create(&dev->control.sem_def);
TU_ASSERT(dev->control.sem_hdl != NULL);
dev->control.mutex_hdl = osal_mutex_create(&dev->control.mutex_def);
TU_ASSERT(dev->control.mutex_hdl != NULL);
memset(dev->itf2drv, 0xff, sizeof(dev->itf2drv)); // invalid mapping
memset(dev->ep2drv , 0xff, sizeof(dev->ep2drv )); // invalid mapping
}
// Class drivers init
for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++) usbh_class_drivers[drv_id].init();
TU_ASSERT(hcd_init());
hcd_int_enable(TUH_OPT_RHPORT);
return true;
}
void setUp(void)
{
ehci_controller_init();
TEST_ASSERT_STATUS( hcd_init());
hostid = RANDOM(CONTROLLER_HOST_NUMBER) + TEST_CONTROLLER_HOST_START_INDEX;
regs = get_operational_register(hostid);
}
//--------------------------------------------------------------------+
// Setup/Teardown + helper declare
//--------------------------------------------------------------------+
void setUp(void)
{
memclr_(usbh_devices, sizeof(usbh_device_info_t)*(TUSB_CFG_HOST_DEVICE_MAX+1));
hcd_init();
dev_addr = 1;
hostid = RANDOM(CONTROLLER_HOST_NUMBER) + TEST_CONTROLLER_HOST_START_INDEX;
helper_usbh_device_emulate(dev_addr , hub_addr, hub_port, hostid, TUSB_SPEED_HIGH);
period_head_arr = get_period_head( hostid, 1 );
p_int_qhd = NULL;
memclr_(&pipe_hdl, sizeof(pipe_handle_t));
}
/** Initialize UHCI hc driver structure
*
* @param[in] instance Memory place to initialize.
* @param[in] regs Address of I/O control registers.
* @param[in] reg_size Size of I/O control registers.
* @param[in] interrupts True if hw interrupts should be used.
* @return Error code.
* @note Should be called only once on any structure.
*
* Initializes memory structures, starts up hw, and launches debugger and
* interrupt fibrils.
*/
int hc_init(hc_t *instance, void *regs, size_t reg_size, bool interrupts)
{
assert(reg_size >= sizeof(uhci_regs_t));
int ret;
#define CHECK_RET_RETURN(ret, message...) \
if (ret != EOK) { \
usb_log_error(message); \
return ret; \
} else (void) 0
instance->hw_interrupts = interrupts;
instance->hw_failures = 0;
/* allow access to hc control registers */
uhci_regs_t *io;
ret = pio_enable(regs, reg_size, (void **)&io);
CHECK_RET_RETURN(ret, "Failed to gain access to registers at %p: %s.\n",
io, str_error(ret));
instance->registers = io;
usb_log_debug(
"Device registers at %p (%zuB) accessible.\n", io, reg_size);
ret = hc_init_mem_structures(instance);
CHECK_RET_RETURN(ret,
"Failed to initialize UHCI memory structures: %s.\n",
str_error(ret));
#undef CHECK_RET_RETURN
hcd_init(&instance->generic, USB_SPEED_FULL,
BANDWIDTH_AVAILABLE_USB11, bandwidth_count_usb11);
instance->generic.private_data = instance;
instance->generic.schedule = hc_schedule;
instance->generic.ep_add_hook = NULL;
hc_init_hw(instance);
if (!interrupts) {
instance->interrupt_emulator =
fibril_create(hc_interrupt_emulator, instance);
fibril_add_ready(instance->interrupt_emulator);
}
(void)hc_debug_checker;
return EOK;
}
//--------------------------------------------------------------------+
// Setup/Teardown + helper declare
//--------------------------------------------------------------------+
void setUp(void)
{
ehci_controller_init();
memclr_(xfer_data, sizeof(xfer_data));
memclr_(usbh_devices, sizeof(usbh_device_info_t)*(TUSB_CFG_HOST_DEVICE_MAX+1));
TEST_ASSERT_STATUS( hcd_init() );
dev_addr = 1;
hostid = RANDOM(CONTROLLER_HOST_NUMBER) + TEST_CONTROLLER_HOST_START_INDEX;
helper_usbh_device_emulate(dev_addr, hub_addr, hub_port, hostid, TUSB_SPEED_HIGH);
async_head = get_async_head( hostid );
//------------- pipe open -------------//
pipe_hdl_bulk = hcd_pipe_open(dev_addr, &desc_ept_bulk_in, TUSB_CLASS_MSC);
TEST_ASSERT_EQUAL(dev_addr, pipe_hdl_bulk.dev_addr);
TEST_ASSERT_EQUAL(TUSB_XFER_BULK, pipe_hdl_bulk.xfer_type);
p_qhd_bulk = &ehci_data.device[ dev_addr -1].qhd[ pipe_hdl_bulk.index ];
}