static void phy_init(int rx_port_sel, int dcm)
{
unsigned int data32;
// Configuring I2C to work in fastmode
hdmirx_wr_dwc( RA_I2CM_PHYG3_MODE, 0x1);
hdmirx_phy_pddq(1);
/* write timebase override and override enable */
hdmirx_wr_phy(OVL_PROT_CTRL, 0x2); //disable overload protect for Philips DVD
hdmirx_wr_phy(REG_HDMI_PHY_CMU_CONFIG,
(rx.phy.phy_cmu_config_force_val != 0) ? rx.phy.phy_cmu_config_force_val :
((rx.phy.lock_thres << 10) | (1 << 9) | (((1 << 9) - 1) & ((rx.phy.cfg_clk * 4) / 1000))));
data32 = 0;
data32 |= 0 << 15; // [15] mpll_short_power_up
data32 |= 0 << 13; // [14:13] mpll_mult
data32 |= 0 << 12; // [12] dis_off_lp
data32 |= rx.phy.fast_switching << 11; // [11] fast_switching
data32 |= 0 << 10; // [10] bypass_afe
data32 |= rx.phy.fsm_enhancement<< 9; // [9] fsm_enhancement
data32 |= 0 << 8; // [8] low_freq_eq
data32 |= 0 << 7; // [7] bypass_aligner
data32 |= dcm << 5; // [6:5] color_depth: 0=8-bit; 1=10-bit; 2=12-bit; 3=16-bit.
data32 |= 0 << 3; // [4:3] sel_tmdsclk: 0=Use chan0 clk; 1=Use chan1 clk; 2=Use chan2 clk; 3=Rsvd.
data32 |= rx.phy.port_select_ovr_en << 2; // [2] port_select_ovr_en
data32 |= rx_port_sel << 0; // [1:0] port_select_ovr
hdmirx_wr_phy( REG_HDMI_PHY_SYSTEM_CONFIG,
(rx.phy.phy_system_config_force_val != 0) ? rx.phy.phy_system_config_force_val : data32);
//phy clock config
hdmirx_phy_pddq(0);
}
static void hdmi_rx_phy_fast_switching( int enable)
{
hdmirx_wr_phy(REG_HDMI_PHY_SYSTEM_CONFIG, hdmirx_rd_phy(REG_HDMI_PHY_SYSTEM_CONFIG) | ((enable & 1) << 11));
}
void phy_init(int rx_port_sel, int dcm)
{
unsigned int data32;
// PDDQ = 1'b1; PHY_RESET = 1'b1;
data32 = 0;
data32 |= 1 << 6; // [6] physvsretmodez
data32 |= 1 << 4; // [5:4] cfgclkfreq
data32 |= rx_port_sel << 2; // [3:2] portselect
data32 |= 1 << 1; // [1] phypddq
data32 |= 1 << 0; // [0] phyreset
hdmirx_wr_dwc(RA_SNPS_PHYG3_CTRL, data32); // DEFAULT: {27'd0, 3'd0, 2'd1}
mdelay(1);
// PDDQ = 1'b1; PHY_RESET = 1'b0;
data32 = 0;
data32 |= 1 << 6; // [6] physvsretmodez
data32 |= 1 << 4; // [5:4] cfgclkfreq
data32 |= rx_port_sel << 2; // [3:2] portselect
data32 |= 1 << 1; // [1] phypddq
data32 |= 0 << 0; // [0] phyreset
hdmirx_wr_dwc(RA_SNPS_PHYG3_CTRL, data32); // DEFAULT: {27'd0, 3'd0, 2'd1}
// Configuring PHY's MPLL
hdmirx_wr_phy(MPLL_PARAMETERS2, 0x2594);
hdmirx_wr_phy(MPLL_PARAMETERS3, 0x395B);
hdmirx_wr_phy(MPLL_PARAMETERS4, 0x3723);
hdmirx_wr_phy(MPLL_PARAMETERS5, 0x54BC);
hdmirx_wr_phy(MPLL_PARAMETERS6, 0x3A9C);
hdmirx_wr_phy(MPLL_PARAMETERS7, 0x310E);
hdmirx_wr_phy(MPLL_PARAMETERS8, 0x2520);
// Configuring I2C to work in fastmode
hdmirx_wr_dwc(RA_I2CM_PHYG3_MODE, 0x1);
/* write timebase override and override enable */
hdmirx_wr_phy(OVL_PROT_CTRL, 0x2); //disable overload protect for Philips DVD
hdmirx_wr_phy(REG_HDMI_PHY_CMU_CONFIG,
(rx.phy.phy_cmu_config_force_val != 0) ? rx.phy.phy_cmu_config_force_val :
((rx.phy.lock_thres << 10) | (1 << 9) | (((1 << 9) - 1) & ((rx.phy.cfg_clk * 4) / 1000))));
data32 = 0;
data32 |= 0 << 15; // [15] mpll_short_power_up
data32 |= 0 << 13; // [14:13] mpll_mult
data32 |= 0 << 12; // [12] dis_off_lp
data32 |= rx.phy.fast_switching << 11; // [11] fast_switching
data32 |= 0 << 10; // [10] bypass_afe
data32 |= rx.phy.fsm_enhancement<< 9; // [9] fsm_enhancement
data32 |= 0 << 8; // [8] low_freq_eq
data32 |= 0 << 7; // [7] bypass_aligner
data32 |= dcm << 5; // [6:5] color_depth: 0=8-bit; 1=10-bit; 2=12-bit; 3=16-bit.
data32 |= 0 << 3; // [4:3] sel_tmdsclk: 0=Use chan0 clk; 1=Use chan1 clk; 2=Use chan2 clk; 3=Rsvd.
data32 |= rx.phy.port_select_ovr_en << 2; // [2] port_select_ovr_en
data32 |= rx_port_sel << 0; // [1:0] port_select_ovr
hdmirx_wr_phy(REG_HDMI_PHY_SYSTEM_CONFIG,
(rx.phy.phy_system_config_force_val != 0) ? rx.phy.phy_system_config_force_val : data32);
// PDDQ = 1'b0; PHY_RESET = 1'b0;
data32 = 0;
data32 |= 1 << 6; // [6] physvsretmodez
data32 |= 1 << 4; // [5:4] cfgclkfreq
data32 |= rx_port_sel << 2; // [3:2] portselect
data32 |= 0 << 1; // [1] phypddq
data32 |= 0 << 0; // [0] phyreset
hdmirx_wr_dwc(RA_SNPS_PHYG3_CTRL, data32); // DEFAULT: {27'd0, 3'd0, 2'd1}
}