int hieth_mdio_write( struct hieth_mdio_local *ld, int phy_addr, int regnum, int val) { int ret = 0; hieth_assert((!(phy_addr & (~0x1F))) && (!(regnum & (~0x1F)))); hieth_trace(4, "phy_addr = %d, regnum = %d", phy_addr, regnum); local_lock(ld); if (!wait_mdio_ready(ld)) { hieth_error("mdio busy"); ret = -1; goto error_exit; } mdio_phywrite(ld, phy_addr, regnum, val); error_exit: local_unlock(ld); return val; }
int hieth_mdio_read(struct hieth_mdio_local *ld, int phy_addr, int regnum) { int val = 0; hieth_assert((!(phy_addr & (~0x1F))) && (!(regnum & (~0x1F)))); local_lock(ld); if (!wait_mdio_ready(ld)) { hieth_error("mdio busy"); goto error_exit; } mdio_start_phyread(ld, phy_addr, regnum); if (wait_mdio_ready(ld)) val = mdio_get_phyread_val(ld); else hieth_error("read timeout"); error_exit: local_unlock(ld); hieth_trace(4, "phy_addr = %d, regnum = %d, val = 0x%04x", phy_addr, regnum, val); return val; }
int hieth_port_reset(struct hieth_netdev_local *ld, int port) { long long chipid = get_chipid(); hieth_assert(port == ld->port); /*soft reset */ if (chipid == _HI3712_V100) { hieth_writel_bits(ld, 1, GLB_SOFT_RESET, HI3712_BITS_ETH_SOFT_RESET); msleep(1); hieth_writel_bits(ld, 0, GLB_SOFT_RESET, HI3712_BITS_ETH_SOFT_RESET); msleep(1); hieth_writel_bits(ld, 1, GLB_SOFT_RESET, HI3712_BITS_ETH_SOFT_RESET); msleep(1); hieth_writel_bits(ld, 0, GLB_SOFT_RESET, HI3712_BITS_ETH_SOFT_RESET); } else { if (ld->port == UP_PORT) { /* Note: sf ip need reset twice */ hieth_writel_bits(ld, 1, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_UP); msleep(1); hieth_writel_bits(ld, 0, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_UP); msleep(1); hieth_writel_bits(ld, 1, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_UP); msleep(1); hieth_writel_bits(ld, 0, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_UP); } else if (ld->port == DOWN_PORT) { /* Note: sf ip need reset twice */ hieth_writel_bits(ld, 1, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_DOWN); msleep(1); hieth_writel_bits(ld, 0, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_DOWN); msleep(1); hieth_writel_bits(ld, 1, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_DOWN); msleep(1); hieth_writel_bits(ld, 0, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_DOWN); } else BUG(); } return 0; }
static int hieth_plat_driver_remove(struct platform_device *pdev) { hieth_assert(hieth_devs_save[UP_PORT] || hieth_devs_save[DOWN_PORT]); free_irq(CONFIG_HIETH_IRQNUM, hieth_devs_save); hieth_platdev_remove_port(pdev, UP_PORT); hieth_platdev_remove_port(pdev, DOWN_PORT); hieth_mdiobus_driver_exit(); hieth_sys_exit(); memset(hieth_devs_save, 0, sizeof(hieth_devs_save)); return 0; }
int hieth_port_reset(struct hieth_netdev_local *ld, int port) { hieth_assert(port == ld->port); /*soft reset*/ if (ld->port == UP_PORT) { /* Note: sf ip need reset twice */ hieth_writel_bits(ld, 1, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_UP); msleep(20); hieth_writel_bits(ld, 0, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_UP); msleep(20); hieth_writel_bits(ld, 1, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_UP); msleep(20); hieth_writel_bits(ld, 0, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_UP); } else if (ld->port == DOWN_PORT) { /* Note: sf ip need reset twice */ hieth_writel_bits(ld, 1, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_DOWN); msleep(20); hieth_writel_bits(ld, 0, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_DOWN); msleep(20); hieth_writel_bits(ld, 1, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_DOWN); msleep(20); hieth_writel_bits(ld, 0, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_DOWN); } else { BUG(); } return 0; }