static int
tegra_uart_probe(device_t dev)
{
struct tegra_softc *sc;
phandle_t node;
uint64_t freq;
int shift;
int rv;
const struct ofw_compat_data *cd;
sc = device_get_softc(dev);
if (!ofw_bus_status_okay(dev))
return (ENXIO);
cd = ofw_bus_search_compatible(dev, compat_data);
if (cd->ocd_data == 0)
return (ENXIO);
sc->ns8250_base.base.sc_class = (struct uart_class *)cd->ocd_data;
rv = hwreset_get_by_ofw_name(dev, "serial", &sc->reset);
if (rv != 0) {
device_printf(dev, "Cannot get 'serial' reset\n");
return (ENXIO);
}
rv = hwreset_deassert(sc->reset);
if (rv != 0) {
device_printf(dev, "Cannot unreset 'serial' reset\n");
return (ENXIO);
}
node = ofw_bus_get_node(dev);
shift = uart_fdt_get_shift1(node);
rv = clk_get_by_ofw_index(dev, 0, &sc->clk);
if (rv != 0) {
device_printf(dev, "Cannot get UART clock: %d\n", rv);
return (ENXIO);
}
rv = clk_enable(sc->clk);
if (rv != 0) {
device_printf(dev, "Cannot enable UART clock: %d\n", rv);
return (ENXIO);
}
rv = clk_get_freq(sc->clk, &freq);
if (rv != 0) {
device_printf(dev, "Cannot enable UART clock: %d\n", rv);
return (ENXIO);
}
device_printf(dev, "got UART clock: %lld\n", freq);
return (uart_bus_probe(dev, shift, (int)freq, 0, 0));
}
static int
get_fdt_resources(struct tegra_ahci_sc *sc, phandle_t node)
{
int rv;
rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-supply",
&sc->supply_hvdd );
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'hvdd' regulator\n");
return (ENXIO);
}
rv = regulator_get_by_ofw_property(sc->dev, 0, "vddio-supply",
&sc->supply_vddio);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'vddio' regulator\n");
return (ENXIO);
}
rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-supply",
&sc->supply_avdd);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'avdd' regulator\n");
return (ENXIO);
}
rv = regulator_get_by_ofw_property(sc->dev, 0, "target-5v-supply",
&sc->supply_target_5v);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'target-5v' regulator\n");
return (ENXIO);
}
rv = regulator_get_by_ofw_property(sc->dev, 0, "target-12v-supply",
&sc->supply_target_12v);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'target-12v' regulator\n");
return (ENXIO);
}
rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata", &sc->hwreset_sata );
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'sata' reset\n");
return (ENXIO);
}
rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata-oob",
&sc->hwreset_sata_oob);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'sata oob' reset\n");
return (ENXIO);
}
rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata-cold",
&sc->hwreset_sata_cold);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'sata cold' reset\n");
return (ENXIO);
}
rv = phy_get_by_ofw_name(sc->dev, 0, "sata-0", &sc->phy);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'sata' phy\n");
return (ENXIO);
}
rv = clk_get_by_ofw_name(sc->dev, 0, "sata", &sc->clk_sata);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'sata' clock\n");
return (ENXIO);
}
rv = clk_get_by_ofw_name(sc->dev, 0, "sata-oob", &sc->clk_sata_oob);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'sata oob' clock\n");
return (ENXIO);
}
rv = clk_get_by_ofw_name(sc->dev, 0, "cml1", &sc->clk_cml);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'cml1' clock\n");
return (ENXIO);
}
rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'pll_e' clock\n");
return (ENXIO);
}
return (0);
}
static int
get_fdt_resources(struct tegra_xhci_softc *sc, phandle_t node)
{
int rv;
rv = regulator_get_by_ofw_property(sc->dev, 0, "avddio-pex-supply",
&sc->supply_avddio_pex);
if (rv != 0) {
device_printf(sc->dev,
"Cannot get 'avddio-pex' regulator\n");
return (ENXIO);
}
rv = regulator_get_by_ofw_property(sc->dev, 0, "dvddio-pex-supply",
&sc->supply_dvddio_pex);
if (rv != 0) {
device_printf(sc->dev,
"Cannot get 'dvddio-pex' regulator\n");
return (ENXIO);
}
rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-usb-supply",
&sc->supply_avdd_usb);
if (rv != 0) {
device_printf(sc->dev,
"Cannot get 'avdd-usb' regulator\n");
return (ENXIO);
}
rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pll-utmip-supply",
&sc->supply_avdd_pll_utmip);
if (rv != 0) {
device_printf(sc->dev,
"Cannot get 'avdd-pll-utmip' regulator\n");
return (ENXIO);
}
rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pll-erefe-supply",
&sc->supply_avdd_pll_erefe);
if (rv != 0) {
device_printf(sc->dev,
"Cannot get 'avdd-pll-erefe' regulator\n");
return (ENXIO);
}
rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-usb-ss-pll-supply",
&sc->supply_avdd_usb_ss_pll);
if (rv != 0) {
device_printf(sc->dev,
"Cannot get 'avdd-usb-ss-pll' regulator\n");
return (ENXIO);
}
rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-usb-ss-supply",
&sc->supply_hvdd_usb_ss);
if (rv != 0) {
device_printf(sc->dev,
"Cannot get 'hvdd-usb-ss' regulator\n");
return (ENXIO);
}
rv = regulator_get_by_ofw_property(sc->dev, 0,
"hvdd-usb-ss-pll-e-supply", &sc->supply_hvdd_usb_ss_pll_e);
if (rv != 0) {
device_printf(sc->dev,
"Cannot get 'hvdd-usb-ss-pll-e' regulator\n");
return (ENXIO);
}
rv = hwreset_get_by_ofw_name(sc->dev, 0, "xusb_host",
&sc->hwreset_xusb_host);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'xusb_host' reset\n");
return (ENXIO);
}
rv = hwreset_get_by_ofw_name(sc->dev, 0, "xusb_ss",
&sc->hwreset_xusb_ss);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'xusb_ss' reset\n");
return (ENXIO);
}
rv = phy_get_by_ofw_name(sc->dev, 0, "usb2-0", &sc->phy_usb2_0);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'usb2-0' phy\n");
return (ENXIO);
}
rv = phy_get_by_ofw_name(sc->dev, 0, "usb2-1", &sc->phy_usb2_1);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'usb2-1' phy\n");
return (ENXIO);
}
rv = phy_get_by_ofw_name(sc->dev, 0, "usb2-2", &sc->phy_usb2_2);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'usb2-2' phy\n");
return (ENXIO);
}
rv = phy_get_by_ofw_name(sc->dev, 0, "usb3-0", &sc->phy_usb3_0);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'usb3-0' phy\n");
return (ENXIO);
}
rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_host",
&sc->clk_xusb_host);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'xusb_host' clock\n");
return (ENXIO);
}
rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_falcon_src",
&sc->clk_xusb_falcon_src);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'xusb_falcon_src' clock\n");
return (ENXIO);
}
rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_ss",
&sc->clk_xusb_ss);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'xusb_ss' clock\n");
return (ENXIO);
}
rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_hs_src",
&sc->clk_xusb_hs_src);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'xusb_hs_src' clock\n");
return (ENXIO);
}
rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_fs_src",
&sc->clk_xusb_fs_src);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'xusb_fs_src' clock\n");
return (ENXIO);
}
rv = clk_get_by_ofw_index_prop(sc->dev, 0, "freebsd,clock-xusb-gate", 0,
&sc->clk_xusb_gate);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'xusb_gate' clock\n");
return (ENXIO);
}
return (0);
}
static int
aw_ir_attach(device_t dev)
{
struct aw_ir_softc *sc;
hwreset_t rst_apb;
clk_t clk_ir, clk_gate;
int err;
uint32_t val = 0;
clk_ir = clk_gate = NULL;
rst_apb = NULL;
sc = device_get_softc(dev);
sc->dev = dev;
if (bus_alloc_resources(dev, aw_ir_spec, sc->res) != 0) {
device_printf(dev, "could not allocate memory resource\n");
return (ENXIO);
}
switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
case A10_IR:
sc->fifo_size = 16;
break;
case A13_IR:
sc->fifo_size = 64;
break;
}
/* De-assert reset */
if (hwreset_get_by_ofw_name(dev, 0, "apb", &rst_apb) == 0) {
err = hwreset_deassert(rst_apb);
if (err != 0) {
device_printf(dev, "cannot de-assert reset\n");
goto error;
}
}
/* Reset buffer */
aw_ir_buf_reset(sc);
/* Get clocks and enable them */
err = clk_get_by_ofw_name(dev, 0, "apb", &clk_gate);
if (err != 0) {
device_printf(dev, "Cannot get gate clock\n");
goto error;
}
err = clk_get_by_ofw_name(dev, 0, "ir", &clk_ir);
if (err != 0) {
device_printf(dev, "Cannot get IR clock\n");
goto error;
}
/* Set clock rate */
err = clk_set_freq(clk_ir, AW_IR_BASE_CLK, 0);
if (err != 0) {
device_printf(dev, "cannot set IR clock rate\n");
goto error;
}
/* Enable clocks */
err = clk_enable(clk_gate);
if (err != 0) {
device_printf(dev, "Cannot enable clk gate\n");
goto error;
}
err = clk_enable(clk_ir);
if (err != 0) {
device_printf(dev, "Cannot enable IR clock\n");
goto error;
}
if (bus_setup_intr(dev, sc->res[1],
INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_ir_intr, sc,
&sc->intrhand)) {
bus_release_resources(dev, aw_ir_spec, sc->res);
device_printf(dev, "cannot setup interrupt handler\n");
return (ENXIO);
}
/* Enable CIR Mode */
WRITE(sc, AW_IR_CTL, AW_IR_CTL_MD);
/*
* Set clock sample, filter, idle thresholds.
* Frequency sample = 3MHz/128 = 23437.5Hz (42.7us)
*/
val = AW_IR_SAMPLE_128;
val |= (AW_IR_RXFILT_VAL | AW_IR_RXIDLE_VAL);
val |= (AW_IR_ACTIVE_T | AW_IR_ACTIVE_T_C);
WRITE(sc, AW_IR_CIR, val);
/* Invert Input Signal */
WRITE(sc, AW_IR_RXCTL, AW_IR_RXCTL_RPPI);
/* Clear All RX Interrupt Status */
WRITE(sc, AW_IR_RXSTA, AW_IR_RXSTA_CLEARALL);
/*
* Enable RX interrupt in case of overflow, packet end
* and FIFO available.
* RX FIFO Threshold = FIFO size / 2
*/
WRITE(sc, AW_IR_RXINT, AW_IR_RXINT_ROI_EN | AW_IR_RXINT_RPEI_EN |
AW_IR_RXINT_RAI_EN | AW_IR_RXINT_RAL((sc->fifo_size >> 1) - 1));
/* Enable IR Module */
val = READ(sc, AW_IR_CTL);
WRITE(sc, AW_IR_CTL, val | AW_IR_CTL_GEN | AW_IR_CTL_RXEN);
sc->sc_evdev = evdev_alloc();
evdev_set_name(sc->sc_evdev, device_get_desc(sc->dev));
evdev_set_phys(sc->sc_evdev, device_get_nameunit(sc->dev));
evdev_set_id(sc->sc_evdev, BUS_HOST, 0, 0, 0);
evdev_support_event(sc->sc_evdev, EV_SYN);
evdev_support_event(sc->sc_evdev, EV_MSC);
evdev_support_msc(sc->sc_evdev, MSC_SCAN);
err = evdev_register(sc->sc_evdev);
if (err) {
device_printf(dev,
"failed to register evdev: error=%d\n", err);
goto error;
}
return (0);
error:
if (clk_gate != NULL)
clk_release(clk_gate);
if (clk_ir != NULL)
clk_release(clk_ir);
if (rst_apb != NULL)
hwreset_release(rst_apb);
evdev_free(sc->sc_evdev);
sc->sc_evdev = NULL; /* Avoid double free */
bus_release_resources(dev, aw_ir_spec, sc->res);
return (ENXIO);
}
static int
tegra_i2c_attach(device_t dev)
{
int rv, rid;
phandle_t node;
struct tegra_i2c_softc *sc;
uint64_t freq;
sc = device_get_softc(dev);
sc->dev = dev;
node = ofw_bus_get_node(dev);
LOCK_INIT(sc);
/* Get the memory resource for the register mapping. */
rid = 0;
sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (sc->mem_res == NULL) {
device_printf(dev, "Cannot map registers.\n");
rv = ENXIO;
goto fail;
}
/* Allocate our IRQ resource. */
rid = 0;
sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_ACTIVE);
if (sc->irq_res == NULL) {
device_printf(dev, "Cannot allocate interrupt.\n");
rv = ENXIO;
goto fail;
}
/* FDT resources. */
rv = clk_get_by_ofw_name(dev, 0, "div-clk", &sc->clk);
if (rv != 0) {
device_printf(dev, "Cannot get i2c clock: %d\n", rv);
goto fail;
}
rv = hwreset_get_by_ofw_name(sc->dev, 0, "i2c", &sc->reset);
if (rv != 0) {
device_printf(sc->dev, "Cannot get i2c reset\n");
return (ENXIO);
}
rv = OF_getencprop(node, "clock-frequency", &sc->bus_freq,
sizeof(sc->bus_freq));
if (rv != sizeof(sc->bus_freq)) {
sc->bus_freq = 100000;
goto fail;
}
/* Request maximum frequency for I2C block 136MHz (408MHz / 3). */
rv = clk_set_freq(sc->clk, 136000000, CLK_SET_ROUND_DOWN);
if (rv != 0) {
device_printf(dev, "Cannot set clock frequency\n");
goto fail;
}
rv = clk_get_freq(sc->clk, &freq);
if (rv != 0) {
device_printf(dev, "Cannot get clock frequency\n");
goto fail;
}
sc->core_freq = (uint32_t)freq;
rv = clk_enable(sc->clk);
if (rv != 0) {
device_printf(dev, "Cannot enable clock: %d\n", rv);
goto fail;
}
/* Init hardware. */
rv = tegra_i2c_hw_init(sc);
if (rv) {
device_printf(dev, "tegra_i2c_activate failed\n");
goto fail;
}
/* Setup interrupt. */
rv = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
NULL, tegra_i2c_intr, sc, &sc->irq_h);
if (rv) {
device_printf(dev, "Cannot setup interrupt.\n");
goto fail;
}
/* Attach the iicbus. */
sc->iicbus = device_add_child(dev, "iicbus", -1);
if (sc->iicbus == NULL) {
device_printf(dev, "Could not allocate iicbus instance.\n");
rv = ENXIO;
goto fail;
}
/* Probe and attach the iicbus. */
return (bus_generic_attach(dev));
fail:
if (sc->irq_h != NULL)
bus_teardown_intr(dev, sc->irq_res, sc->irq_h);
if (sc->irq_res != NULL)
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
if (sc->mem_res != NULL)
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
LOCK_DESTROY(sc);
return (rv);
}
static int
usbphy_attach(device_t dev)
{
struct usbphy_softc * sc;
int rid, rv;
phandle_t node;
sc = device_get_softc(dev);
sc->dev = dev;
rid = 0;
sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE | RF_SHAREABLE);
if (sc->mem_res == NULL) {
device_printf(dev, "Cannot allocate memory resources\n");
return (ENXIO);
}
rid = 1;
sc->pads_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE | RF_SHAREABLE);
if (sc->mem_res == NULL) {
device_printf(dev, "Cannot allocate memory resources\n");
return (ENXIO);
}
node = ofw_bus_get_node(dev);
rv = hwreset_get_by_ofw_name(sc->dev, 0, "usb", &sc->reset_usb);
if (rv != 0) {
device_printf(dev, "Cannot get 'usb' reset\n");
return (ENXIO);
}
rv = hwreset_get_by_ofw_name(sc->dev, 0, "utmi-pads", &sc->reset_pads);
if (rv != 0) {
device_printf(dev, "Cannot get 'utmi-pads' reset\n");
return (ENXIO);
}
rv = clk_get_by_ofw_name(sc->dev, 0, "reg", &sc->clk_reg);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'reg' clock\n");
return (ENXIO);
}
rv = clk_get_by_ofw_name(sc->dev, 0, "pll_u", &sc->clk_pllu);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'pll_u' clock\n");
return (ENXIO);
}
rv = clk_get_by_ofw_name(sc->dev, 0, "utmi-pads", &sc->clk_pads);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'utmi-pads' clock\n");
return (ENXIO);
}
rv = hwreset_deassert(sc->reset_usb);
if (rv != 0) {
device_printf(dev, "Cannot unreset 'usb' reset\n");
return (ENXIO);
}
rv = clk_enable(sc->clk_pllu);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'pllu' clock\n");
return (ENXIO);
}
rv = clk_enable(sc->clk_reg);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'reg' clock\n");
return (ENXIO);
}
if (OF_hasprop(node, "nvidia,has-utmi-pad-registers"))
sc->have_utmi_regs = true;
sc->dr_mode = usb_get_dr_mode(dev, node, "dr_mode");
if (sc->dr_mode == USB_DR_MODE_UNKNOWN)
sc->dr_mode = USB_DR_MODE_HOST;
sc->ifc_type = usb_get_ifc_mode(dev, node, "phy_type");
/* We supports only utmi phy mode for now .... */
if (sc->ifc_type != USB_IFC_TYPE_UTMI) {
device_printf(dev, "Unsupported phy type\n");
return (ENXIO);
}
rv = usbphy_utmi_read_params(sc, node);
if (rv < 0)
return rv;
if (OF_hasprop(node, "vbus-supply")) {
rv = regulator_get_by_ofw_property(sc->dev, 0, "vbus-supply",
&sc->supply_vbus);
if (rv != 0) {
device_printf(sc->dev,
"Cannot get \"vbus\" regulator\n");
return (ENXIO);
}
rv = regulator_enable(sc->supply_vbus);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable \"vbus\" regulator\n");
return (rv);
}
}
phy_register_provider(dev);
return (0);
}
