void jump_to_image_no_args(void)
{
typedef void (*image_entry_noargs_t)(void)__attribute__ ((noreturn));
image_entry_noargs_t image_entry =
(image_entry_noargs_t) image_entry_point;
image_entry();
}
static void jump_to_image_no_args(void)
{
typedef void (*image_entry_noargs_t)(void)__attribute__ ((noreturn));
image_entry_noargs_t image_entry =
(image_entry_noargs_t) spl_image.entry_point;
debug("image entry point: 0x%X\n", spl_image.entry_point);
image_entry();
}
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
typedef void __noreturn (*image_entry_noargs_t)(void);
image_entry_noargs_t image_entry =
(image_entry_noargs_t)spl_image->entry_point;
debug("image entry point: 0x%lX\n", spl_image->entry_point);
image_entry();
}
static void __noreturn jump_to_image_linux(void *arg)
{
debug("Entering kernel arg pointer: 0x%p\n", arg);
typedef void (*image_entry_arg_t)(int, int, void *)
__attribute__ ((noreturn));
image_entry_arg_t image_entry =
(image_entry_arg_t) spl_image.entry_point;
cleanup_before_linux();
image_entry(0, CONFIG_MACH_TYPE, arg);
}
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
typedef void __noreturn (*image_entry_noargs_t)(u32 *);
image_entry_noargs_t image_entry =
(image_entry_noargs_t) spl_image->entry_point;
debug("image entry point: 0x%X\n", spl_image->entry_point);
/* Pass the saved boot_params from rom code */
image_entry((u32 *)&gd->arch.omap_boot_params);
}
void __noreturn jump_to_image_linux(void *arg)
{
debug("Entering kernel arg pointer: 0x%p\n", arg);
typedef void (*image_entry_arg_t)(void *, ulong r4, ulong r5, ulong r6,
ulong r7, ulong r8, ulong r9)
__attribute__ ((noreturn));
image_entry_arg_t image_entry =
(image_entry_arg_t)spl_image.entry_point;
image_entry(arg, 0, 0, EPAPR_MAGIC, CONFIG_SYS_BOOTMAPSZ, 0, 0);
}
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
typedef void __noreturn (*image_entry_noargs_t)(u32 *);
image_entry_noargs_t image_entry =
(image_entry_noargs_t) spl_image->entry_point;
u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
debug("image entry point: 0x%X\n", spl_image->entry_point);
/* Pass the saved boot_params from rom code */
image_entry((u32 *)boot_params);
}
static void __noreturn jump_to_image_no_args(void)
{
typedef void __noreturn (*image_entry_noargs_t)(u32 *);
image_entry_noargs_t image_entry =
(image_entry_noargs_t) spl_image.entry_point;
debug("image entry point: 0x%X\n", spl_image.entry_point);
/* Pass the saved boot_params from rom code */
#if defined(CONFIG_VIRTIO) || defined(CONFIG_ZEBU)
image_entry = (image_entry_noargs_t)0x80100000;
#endif
u32 boot_params_ptr_addr = (u32)&boot_params_ptr;
image_entry((u32 *)boot_params_ptr_addr);
}
void __noreturn jump_to_image_linux(void *arg)
{
unsigned long machid = 0xffffffff;
#ifdef CONFIG_MACH_TYPE
machid = CONFIG_MACH_TYPE;
#endif
debug("Entering kernel arg pointer: 0x%p\n", arg);
typedef void (*image_entry_arg_t)(int, int, void *)
__attribute__ ((noreturn));
image_entry_arg_t image_entry =
(image_entry_arg_t)(uintptr_t) spl_image.entry_point;
cleanup_before_linux();
image_entry(0, machid, arg);
}
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
typedef void __noreturn (*image_entry_noargs_t)(void);
image_entry_noargs_t image_entry =
(image_entry_noargs_t)spl_image->entry_point;
debug("image entry point: 0x%lX\n", spl_image->entry_point);
#if defined(CONFIG_ARMV8_SPIN_TABLE) && defined(CONFIG_ARMV8_MULTIENTRY)
/*
* Release all slave cores from CPU_RELEASE_ADDR so they could
* arrive to the spin-table code in start.S of the u-boot
*/
*(ulong *)CPU_RELEASE_ADDR = (ulong)spl_image->entry_point;
#endif
image_entry();
}
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
typedef void __noreturn (*image_entry_noargs_t)(u32 *);
image_entry_noargs_t image_entry =
(image_entry_noargs_t) spl_image->entry_point;
#ifdef CONFIG_HW_WATCHDOG
WATCHDOG_RESET();
#endif
#ifdef CONFIG_SPL_CHECKSUM_NEXT_IMAGE
u32 calculated_crc;
if (spl_image->crc_size != 0) {
#if defined(CONFIG_SPL_SDRAM_ECC_PADDING) && !defined(CONFIG_SPL_SPI_XIP)
/*
* do additional memory initialization / padding to avoid
* the false double bit error (DBE) during read back
* (for checksum purpose) when ECC is enabled
*/
debug("Padding the SDRAM to avoid false ECC DBE\n");
memset((unsigned char *)
(spl_image->entry_point + spl_image->crc_size),
0, CONFIG_SPL_SDRAM_ECC_PADDING);
#endif
debug("Verifying Checksum ... ");
calculated_crc = crc32_wd(0,
(unsigned char *)spl_image->entry_point,
spl_image->crc_size, CHUNKSZ_CRC32);
if (calculated_crc != spl_image->crc) {
puts("Bad image with mismatched CRC\n");
debug("CRC calculate from 0x%08x "
"with length 0x%08x\n",
spl_image->entry_point, spl_image->size);
debug("CRC Result : Expected 0x%08x "
"Calculated 0x%08x\n",
spl_image->crc, calculated_crc);
hang();
} else
debug("OK\n");
}
#endif
#if (CONFIG_PRELOADER_SDRAM_SCRUB_REMAIN_REGION == 1)
/* Ensure scrubbing finished before hand over to next stage */
sdram_scrub_remain_region_finish();
#endif /* CONFIG_PRELOADER_SDRAM_SCRUB_REMAIN_REGION */
debug("image entry point: 0x%X\n", spl_image->entry_point);
/* Pass the saved boot_params from rom code */
#if defined(CONFIG_VIRTIO) || defined(CONFIG_ZEBU)
image_entry = (image_entry_noargs_t)0x80100000;
#endif
#if defined(CONFIG_SOCFPGA) && (CONFIG_PRELOADER_STATE_REG_ENABLE == 1)
/* to indicate a successful run */
writel(CONFIG_PRELOADER_STATE_VALID, CONFIG_PRELOADER_STATE_REG);
#endif
#ifdef CONFIG_HW_WATCHDOG
WATCHDOG_RESET();
#endif
image_entry((u32 *)boot_params_ptr);
}
