void
ioapic_set_legacy_irqmap(int irq, int gsi, enum intr_trigger trig,
enum intr_polarity pola)
{
struct ioapic_irqinfo *info;
struct ioapic_irqmap *map;
void *ioaddr;
int pin, cpuid;
KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
if (irq > ioapic_abi_legacy_irq_max)
ioapic_abi_legacy_irq_max = irq;
cpuid = ioapic_abi_gsi_cpuid(irq, gsi);
map = &ioapic_irqmaps[cpuid][irq];
KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
map->im_type = IOAPIC_IMT_LEGACY;
map->im_gsi = gsi;
map->im_trig = trig;
map->im_pola = pola;
if (bootverbose) {
kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n",
irq, map->im_gsi,
intr_str_trigger(map->im_trig),
intr_str_polarity(map->im_pola));
}
pin = ioapic_gsi_pin(map->im_gsi);
ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
info = &ioapic_irqs[irq];
imen_lock();
info->io_addr = ioaddr;
info->io_idx = IOAPIC_REDTBL + (2 * pin);
info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
if (map->im_trig == INTR_TRIGGER_LEVEL)
info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
map->im_trig, map->im_pola, cpuid);
imen_unlock();
}
static void
ioapic_abi_intr_teardown(int intr)
{
const struct ioapic_irqmap *map;
int vector, select;
uint32_t value;
register_t ef;
KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
("ioapic teardown, invalid irq %d\n", intr));
map = &ioapic_irqmaps[mycpuid][intr];
KASSERT(IOAPIC_IMT_ISHWI(map),
("ioapic teardown, not hwi irq %d, type %d, cpu%d",
intr, map->im_type, mycpuid));
if (map->im_type != IOAPIC_IMT_LEGACY)
return;
KASSERT(ioapic_irqs[intr].io_addr != NULL,
("ioapic teardown, no GSI information, irq %d\n", intr));
ef = read_rflags();
cpu_disable_intr();
/*
* Teardown an interrupt vector. The vector should already be
* installed in the cpu's IDT, but make sure.
*/
IOAPIC_INTRDIS(intr);
vector = IDT_OFFSET + intr;
/*
* In order to avoid losing an EOI for a level interrupt, which
* is vector based, make sure that the IO APIC is programmed for
* edge-triggering first, then reprogrammed with the new vector.
* This should clear the IRR bit.
*/
imen_lock();
select = ioapic_irqs[intr].io_idx;
value = ioapic_read(ioapic_irqs[intr].io_addr, select);
ioapic_write(ioapic_irqs[intr].io_addr, select,
(value & ~APIC_TRIGMOD_MASK));
ioapic_write(ioapic_irqs[intr].io_addr, select,
(value & ~IOART_INTVEC) | vector);
imen_unlock();
write_rflags(ef);
}
static void
ioapic_abi_intr_setup(int intr, int flags)
{
const struct ioapic_irqmap *map;
int vector, select;
uint32_t value;
register_t ef;
KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
("ioapic setup, invalid irq %d", intr));
map = &ioapic_irqmaps[mycpuid][intr];
KASSERT(IOAPIC_IMT_ISHWI(map),
("ioapic setup, not hwi irq %d, type %d, cpu%d",
intr, map->im_type, mycpuid));
if (map->im_type != IOAPIC_IMT_LEGACY)
return;
KASSERT(ioapic_irqs[intr].io_addr != NULL,
("ioapic setup, no GSI information, irq %d", intr));
ef = read_rflags();
cpu_disable_intr();
vector = IDT_OFFSET + intr;
/*
* Now reprogram the vector in the IO APIC. In order to avoid
* losing an EOI for a level interrupt, which is vector based,
* make sure that the IO APIC is programmed for edge-triggering
* first, then reprogrammed with the new vector. This should
* clear the IRR bit.
*/
imen_lock();
select = ioapic_irqs[intr].io_idx;
value = ioapic_read(ioapic_irqs[intr].io_addr, select);
value |= IOART_INTMSET;
ioapic_write(ioapic_irqs[intr].io_addr, select,
(value & ~APIC_TRIGMOD_MASK));
ioapic_write(ioapic_irqs[intr].io_addr, select,
(value & ~IOART_INTVEC) | vector);
imen_unlock();
IOAPIC_INTREN(intr);
write_rflags(ef);
}
int
ioapic_conf_legacy_extint(int irq)
{
struct ioapic_irqinfo *info;
struct ioapic_irqmap *map;
void *ioaddr;
int pin, error, vec;
/* XXX only irq0 is allowed */
KKASSERT(irq == 0);
vec = IDT_OFFSET + irq;
if (ioapic_abi_extint_irq == irq)
return 0;
else if (ioapic_abi_extint_irq >= 0)
return EEXIST;
error = icu_ioapic_extint(irq, vec);
if (error)
return error;
/* ExtINT is always targeted to cpu0 */
map = &ioapic_irqmaps[0][irq];
KKASSERT(map->im_type == IOAPIC_IMT_RESERVED ||
map->im_type == IOAPIC_IMT_LEGACY);
if (map->im_type == IOAPIC_IMT_LEGACY) {
if (map->im_flags & IOAPIC_IMF_CONF)
return EEXIST;
}
ioapic_abi_extint_irq = irq;
map->im_type = IOAPIC_IMT_LEGACY;
map->im_trig = INTR_TRIGGER_EDGE;
map->im_pola = INTR_POLARITY_HIGH;
map->im_flags = IOAPIC_IMF_CONF;
map->im_gsi = ioapic_extpin_gsi();
KKASSERT(map->im_gsi >= 0);
if (bootverbose) {
kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n",
irq, map->im_gsi,
intr_str_trigger(map->im_trig),
intr_str_polarity(map->im_pola));
}
pin = ioapic_gsi_pin(map->im_gsi);
ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
info = &ioapic_irqs[irq];
imen_lock();
info->io_addr = ioaddr;
info->io_idx = IOAPIC_REDTBL + (2 * pin);
info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
ioapic_extpin_setup(ioaddr, pin, vec);
imen_unlock();
return 0;
}
static void
ioapic_abi_legacy_intr_config(int irq, enum intr_trigger trig,
enum intr_polarity pola)
{
struct ioapic_irqinfo *info;
struct ioapic_irqmap *map = NULL;
void *ioaddr;
int pin, cpuid;
KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
KKASSERT(irq >= 0 && irq < ioapic_abi_legacy_irq_max);
for (cpuid = 0; cpuid < ncpus; ++cpuid) {
map = &ioapic_irqmaps[cpuid][irq];
if (map->im_type == IOAPIC_IMT_LEGACY)
break;
}
KKASSERT(cpuid < ncpus);
#ifdef notyet
if (map->im_flags & IOAPIC_IMF_CONF) {
if (trig != map->im_trig) {
panic("ioapic_intr_config: trig %s -> %s\n",
intr_str_trigger(map->im_trig),
intr_str_trigger(trig));
}
if (pola != map->im_pola) {
panic("ioapic_intr_config: pola %s -> %s\n",
intr_str_polarity(map->im_pola),
intr_str_polarity(pola));
}
return;
}
#endif
map->im_flags |= IOAPIC_IMF_CONF;
if (trig == map->im_trig && pola == map->im_pola)
return;
if (bootverbose) {
kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n",
irq, map->im_gsi,
intr_str_trigger(map->im_trig),
intr_str_polarity(map->im_pola),
intr_str_trigger(trig),
intr_str_polarity(pola));
}
map->im_trig = trig;
map->im_pola = pola;
pin = ioapic_gsi_pin(map->im_gsi);
ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
info = &ioapic_irqs[irq];
imen_lock();
info->io_flags &= ~IOAPIC_IRQI_FLAG_LEVEL;
if (map->im_trig == INTR_TRIGGER_LEVEL)
info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
map->im_trig, map->im_pola, cpuid);
imen_unlock();
}
void
ioapic_set_legacy_irqmap(int irq, int gsi, enum intr_trigger trig,
enum intr_polarity pola)
{
struct ioapic_irqinfo *info;
struct ioapic_irqmap *map;
void *ioaddr;
int pin, cpuid;
KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
KKASSERT(irq >= 0);
if (irq >= IOAPIC_HWI_VECTORS) {
/*
* Some BIOSes seem to assume that all 256 IDT vectors
* could be used, while we limit the available IDT
* vectors to 192; find an unused IRQ for this GSI.
*/
irq = ioapic_find_unused_irqmap(gsi);
if (irq < 0) {
kprintf("failed to find unused irq for gsi %d, "
"overflow\n", gsi);
return;
}
}
KKASSERT(irq < IOAPIC_HWI_VECTORS);
cpuid = ioapic_abi_gsi_cpuid(irq, gsi);
map = &ioapic_irqmaps[cpuid][irq];
if (map->im_type != IOAPIC_IMT_UNUSED) {
/*
* There are so many IOAPICs, that 1:1 mapping
* of GSI and IRQ hits SYSCALL entry.
*/
irq = ioapic_find_unused_irqmap(gsi);
if (irq < 0) {
kprintf("failed to find unused irq for gsi %d, "
"conflict\n", gsi);
return;
}
KKASSERT(irq < IOAPIC_HWI_VECTORS);
cpuid = ioapic_abi_gsi_cpuid(irq, gsi);
map = &ioapic_irqmaps[cpuid][irq];
}
if (irq > ioapic_abi_legacy_irq_max)
ioapic_abi_legacy_irq_max = irq;
KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
map->im_type = IOAPIC_IMT_LEGACY;
map->im_gsi = gsi;
map->im_trig = trig;
map->im_pola = pola;
if (bootverbose) {
kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n",
irq, map->im_gsi,
intr_str_trigger(map->im_trig),
intr_str_polarity(map->im_pola));
}
pin = ioapic_gsi_pin(map->im_gsi);
ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
info = &ioapic_irqs[irq];
imen_lock();
info->io_addr = ioaddr;
info->io_idx = IOAPIC_REDTBL + (2 * pin);
info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
if (map->im_trig == INTR_TRIGGER_LEVEL)
info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
map->im_trig, map->im_pola, cpuid);
imen_unlock();
}
