void imx233_touchscreen_enable(bool enable)
{
enter_state(TOUCH_STATE_WAIT);
imx233_lradc_set_channel_irq_callback(touch_chan, &touch_channel_irq);
imx233_icoll_enable_interrupt(INT_SRC_LRADC_CHx(touch_chan), enable);
imx233_icoll_enable_interrupt(INT_SRC_TOUCH_DETECT, enable);
}
void power_init(void)
{
/* setup vbusvalid parameters: set threshold to 4v and power up comparators */
__REG_CLR(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__VBUSVALID_TRSH_BM;
__REG_SET(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__VBUSVALID_TRSH_4V |
HW_POWER_5VCTRL__PWRUP_VBUS_CMPS;
/* enable vbusvalid detection method for the dcdc (improves efficiency) */
__REG_SET(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__VBUSVALID_5VDETECT;
/* clear vbusvalid irq and set correct polarity */
__REG_CLR(HW_POWER_CTRL) = HW_POWER_CTRL__VBUSVALID_IRQ;
if(HW_POWER_STS & HW_POWER_STS__VBUSVALID)
__REG_CLR(HW_POWER_CTRL) = HW_POWER_CTRL__POLARITY_VBUSVALID;
else
__REG_SET(HW_POWER_CTRL) = HW_POWER_CTRL__POLARITY_VBUSVALID;
__REG_SET(HW_POWER_CTRL) = HW_POWER_CTRL__ENIRQ_VBUS_VALID;
imx233_icoll_enable_interrupt(INT_SRC_VDD5V, true);
/* setup linear regulator offsets to 25 mV below to prevent contention between
* linear regulators and DCDC */
__FIELD_SET(HW_POWER_VDDDCTRL, LINREG_OFFSET, 2);
__FIELD_SET(HW_POWER_VDDACTRL, LINREG_OFFSET, 2);
__FIELD_SET(HW_POWER_VDDIOCTRL, LINREG_OFFSET, 2);
/* enable a few bits controlling the DC-DC as recommended by Freescale */
__REG_SET(HW_POWER_LOOPCTRL) = HW_POWER_LOOPCTRL__TOGGLE_DIF |
HW_POWER_LOOPCTRL__EN_CM_HYST;
__FIELD_SET(HW_POWER_LOOPCTRL, EN_RCSCALE, HW_POWER_LOOPCTRL__EN_RCSCALE__2X);
}
void imx233_lcdif_init(void)
{
imx233_reset_block(&HW_LCDIF_CTRL);
#if IMX233_SUBTARGET >= 3700
imx233_icoll_enable_interrupt(INT_SRC_LCDIF_ERROR, true);
#endif
}
static enum imx233_dcp_error_t imx233_dcp_job(int ch)
{
/* if IRQs are not enabled, don't enable channel interrupt and do some polling */
bool irq_enabled = irq_enabled();
/* enable channel, clear interrupt, enable interrupt */
imx233_icoll_enable_interrupt(INT_SRC_DCP, true);
if(irq_enabled)
__REG_SET(HW_DCP_CTRL) = HW_DCP_CTRL__CHANNEL_INTERRUPT_ENABLE(ch);
__REG_CLR(HW_DCP_STAT) = HW_DCP_STAT__IRQ(ch);
__REG_SET(HW_DCP_CHANNELCTRL) = HW_DCP_CHANNELCTRL__ENABLE_CHANNEL(ch);
/* write back packet */
commit_discard_dcache_range(&channel_packet[ch], sizeof(struct imx233_dcp_packet_t));
/* write 1 to semaphore to run job */
HW_DCP_CHxCMDPTR(ch) = (uint32_t)PHYSICAL_ADDR(&channel_packet[ch]);
HW_DCP_CHxSEMA(ch) = 1;
/* wait completion */
if(irq_enabled)
semaphore_wait(&channel_sema[ch], TIMEOUT_BLOCK);
else
while(__XTRACT_EX(HW_DCP_CHxSEMA(ch), HW_DCP_CHxSEMA__VALUE))
udelay(10);
/* disable channel and interrupt */
__REG_CLR(HW_DCP_CTRL) = HW_DCP_CTRL__CHANNEL_INTERRUPT_ENABLE(ch);
__REG_CLR(HW_DCP_CHANNELCTRL) = HW_DCP_CHANNELCTRL__ENABLE_CHANNEL(ch);
/* read status */
return get_error_status(ch);
}
enum imx233_i2c_error_t imx233_i2c_end(unsigned timeout)
{
if(i2c_nr_stages == 0)
return I2C_ERROR;
i2c_stage[i2c_nr_stages - 1].dma.cmd |= BM_APB_CHx_CMD_SEMAPHORE | BM_APB_CHx_CMD_IRQONCMPLT;
BF_CLR(I2C_CTRL1, ALL_IRQ);
imx233_dma_reset_channel(APB_I2C);
imx233_icoll_enable_interrupt(INT_SRC_I2C_DMA, true);
imx233_icoll_enable_interrupt(INT_SRC_I2C_ERROR, true);
imx233_dma_enable_channel_interrupt(APB_I2C, true);
imx233_dma_start_command(APB_I2C, &i2c_stage[0].dma);
enum imx233_i2c_error_t ret;
if(semaphore_wait(&i2c_sema, timeout) == OBJ_WAIT_TIMEDOUT)
{
imx233_dma_reset_channel(APB_I2C);
imx233_i2c_reset();
ret = I2C_TIMEOUT;
}
else if(BF_RD(I2C_CTRL1, MASTER_LOSS_IRQ))
ret = I2C_MASTER_LOSS;
else if(BF_RD(I2C_CTRL1, NO_SLAVE_ACK_IRQ))
{
/* the core doesn't like this error, this is a workaround to prevent lock up */
#if IMX233_SUBTARGET >= 3780
BF_SET(I2C_CTRL1, CLR_GOT_A_NAK);
#endif
imx233_dma_reset_channel(APB_I2C);
imx233_i2c_reset();
ret = I2C_NO_SLAVE_ACK;
}
else if(BF_RD(I2C_CTRL1, EARLY_TERM_IRQ))
ret = I2C_SLAVE_NAK;
else
ret = imx233_i2c_finalize();
/* sleep */
BF_SET(I2C_CTRL0, CLKGATE);
mutex_unlock(&i2c_mutex);
return ret;
}
void imx233_power_init(void)
{
#if IMX233_SUBTARGET >= 3700
BF_CLR(POWER_MINPWR, HALF_FETS);
#endif
/* setup vbusvalid parameters: set threshold to 4v and power up comparators */
BF_CS(POWER_5VCTRL, VBUSVALID_TRSH(1));
#if IMX233_SUBTARGET >= 3780
BF_SET(POWER_5VCTRL, PWRUP_VBUS_CMPS);
#else
BF_SET(POWER_5VCTRL, OTG_PWRUP_CMPS);
#endif
/* enable vbusvalid detection method for the dcdc (improves efficiency) */
BF_SET(POWER_5VCTRL, VBUSVALID_5VDETECT);
/* disable shutdown on 5V fail */
BF_CLR(POWER_5VCTRL, PWDN_5VBRNOUT);
#ifdef USE_VBUSVALID
/* make sure VBUSVALID is unlocked */
BF_CLR(POWER_DEBUG, VBUSVALIDPIOLOCK);
/* clear vbusvalid irq and set correct polarity */
BF_CLR(POWER_CTRL, VBUSVALID_IRQ);
if(BF_RD(POWER_STS, VBUSVALID))
BF_CLR(POWER_CTRL, POLARITY_VBUSVALID);
else
BF_SET(POWER_CTRL, POLARITY_VBUSVALID);
BF_SET(POWER_CTRL, ENIRQ_VBUS_VALID);
/* make sure old detection way is not enabled */
BF_CLR(POWER_CTRL, ENIRQ_VDD5V_GT_VDDIO);
#else
BF_CLR(POWER_CTRL, VDD5V_GT_VDDIO_IRQ);
if(BF_RD(POWER_STS, VDD5V_GT_VDDIO))
BF_CLR(POWER_CTRL, POLARITY_VDD5V_GT_VDDIO);
else
BF_SET(POWER_CTRL, POLARITY_VDD5V_GT_VDDIO);
BF_SET(POWER_CTRL, ENIRQ_VDD5V_GT_VDDIO);
/* make the vbusvalid detection way is not enabled */
#if IMX233_SUBTARGET >= 3700
BF_CLR(POWER_CTRL, ENIRQ_VBUS_VALID);
#endif
#endif
/* the VDD5V IRQ is shared by several sources, disable them */
#if IMX233_SUBTARGET >= 3700
BF_CLR(POWER_CTRL, ENIRQ_PSWITCH);
BF_CLR(POWER_CTRL, ENIRQ_DC_OK);
#if IMX233_SUBTARGET < 3780
BF_CLR(POWER_CTRL, ENIRQ_LINREG_OK);
#endif /* IMX233_SUBTARGET < 3780 */
#endif /* IMX233_SUBTARGET >= 3700 */
imx233_icoll_enable_interrupt(INT_SRC_VDD5V, true);
}
void imx233_timrot_setup(unsigned timer_nr, bool reload, unsigned count,
unsigned src, unsigned prescale, bool polarity, imx233_timer_fn_t fn)
{
int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
/* only enable interrupt if function is set */
bool irq = fn != NULL;
timer_fns[timer_nr] = fn;
/* make sure we start from stop state */
HW_TIMROT_TIMCTRLn(timer_nr) = BF_OR2(TIMROT_TIMCTRLn,
SELECT(BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK), UPDATE(1));
/* write count and take effect immediately with UPDATE
* manual says count-1 for reload timers */
HW_TIMROT_TIMCOUNTn(timer_nr) = reload ? count - 1 : count;
/* start timer */
HW_TIMROT_TIMCTRLn(timer_nr) = BF_OR6(TIMROT_TIMCTRLn, SELECT(src),
PRESCALE(prescale), POLARITY(polarity), RELOAD(reload), IRQ(irq),
IRQ_EN(irq));
imx233_icoll_enable_interrupt(INT_SRC_TIMER(timer_nr), irq);
restore_interrupt(oldstatus);
}
