void setup_arch(void) {
setup_memory_map();
finish_e820_parsing();
max_pfn = e820_end_of_ram_pfn();
/* preallocate 4k for mptable mpc */
/*
early_reserve_e820_mpc_new();
*/
/* update e820 for memory not covered by WB MTRRs */
/*
mtrr_bp_init();
if (mtrr_trim_uncached_memory(max_pfn)) {
max_pfn = e820_end_of_ram_pfn();
}
*/
/* max_low_pfn get updated here */
find_low_pfn_range();
printk(KERN_DEBUG "initial memory mapped : 0 - %08lx\n",
max_pfn_mapped<<PAGE_SHIFT);
max_low_pfn_mapped = init_memory_mapping(0, max_low_pfn<<PAGE_SHIFT);
max_pfn_mapped = max_low_pfn_mapped;
initmem_init(0, max_pfn);
}
/* Warning, IO base is not yet inited */
void __init setup_arch(char **cmdline_p)
{
*cmdline_p = boot_command_line;
/* so udelay does something sensible, assume <= 1000 bogomips */
loops_per_jiffy = 500000000 / HZ;
unflatten_device_tree();
check_for_initrd();
if (ppc_md.init_early)
ppc_md.init_early();
find_legacy_serial_ports();
smp_setup_cpu_maps();
/* Register early console */
register_early_udbg_console();
xmon_setup();
/*
* Set cache line size based on type of cpu as a default.
* Systems with OF can look in the properties on the cpu node(s)
* for a possibly more accurate value.
*/
dcache_bsize = cur_cpu_spec->dcache_bsize;
icache_bsize = cur_cpu_spec->icache_bsize;
ucache_bsize = 0;
if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
ucache_bsize = icache_bsize = dcache_bsize;
if (ppc_md.panic)
setup_panic();
init_mm.start_code = (unsigned long)_stext;
init_mm.end_code = (unsigned long) _etext;
init_mm.end_data = (unsigned long) _edata;
init_mm.brk = klimit;
exc_lvl_early_init();
irqstack_early_init();
initmem_init();
if ( ppc_md.progress ) ppc_md.progress("setup_arch: initmem", 0x3eab);
#ifdef CONFIG_DUMMY_CONSOLE
conswitchp = &dummy_con;
#endif
if (ppc_md.setup_arch)
ppc_md.setup_arch();
if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab);
paging_init();
/* Initialize the MMU context management stuff */
mmu_context_init();
}
