void __init ppc4xx_pic_init(void) { int i; #if XPAR_XINTC_USE_DCR == 0 intc = ioremap(XPAR_INTC_0_BASEADDR, 32); printk(KERN_INFO "Xilinx INTC #0 at 0x%08lX mapped to 0x%08lX\n", (unsigned long) XPAR_INTC_0_BASEADDR, (unsigned long) intc); #else printk(KERN_INFO "Xilinx INTC #0 at 0x%08lX (DCR)\n", (unsigned long) XPAR_INTC_0_BASEADDR); #endif /* * Disable all external interrupts until they are * explicity requested. */ intc_out_be32(intc + IER, 0); /* Acknowledge any pending interrupts just in case. */ intc_out_be32(intc + IAR, ~(u32) 0); /* Turn on the Master Enable. */ intc_out_be32(intc + MER, 0x3UL); ppc_md.get_irq = xilinx_pic_get_irq; for (i = 0; i < NR_IRQS; ++i) irq_desc[i].handler = &xilinx_intc; }
static void xilinx_intc_disable_and_ack(unsigned int irq) { unsigned long mask = (0x00000001 << (irq & 31)); pr_debug("disable_and_ack: %d\n", irq); intc_out_be32(intc + CIE, mask); if (!(irq_desc[irq].status & IRQ_LEVEL)) intc_out_be32(intc + IAR, mask); /* ack edge triggered intr */ }
static void xilinx_intc_end(unsigned int irq) { unsigned long mask = (0x00000001 << (irq & 31)); pr_debug("end: %d\n", irq); if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { intc_out_be32(intc + SIE, mask); /* ack level sensitive intr */ if (irq_desc[irq].status & IRQ_LEVEL) intc_out_be32(intc + IAR, mask); } }
static void xilinx_intc_disable(unsigned int irq) { unsigned long mask = (0x00000001 << (irq & 31)); pr_debug("disable: %d\n", irq); intc_out_be32(intc + CIE, mask); }
void __init ppc4xx_pic_init(void) { int i; /* * NOTE: The assumption here is that NR_IRQS is 32 or less * (NR_IRQS is 32 for PowerPC 405 cores by default). */ #if (NR_IRQS > 32) #error NR_IRQS > 32 not supported #endif #if XPAR_XINTC_USE_DCR == 0 intc = ioremap(XPAR_INTC_0_BASEADDR, 32); printk(KERN_INFO "Xilinx INTC #0 at 0x%08lX mapped to 0x%08lX\n", (unsigned long) XPAR_INTC_0_BASEADDR, (unsigned long) intc); #else printk(KERN_INFO "Xilinx INTC #0 at 0x%08lX (DCR)\n", (unsigned long) XPAR_INTC_0_BASEADDR); #endif /* * Disable all external interrupts until they are * explicitly requested. */ intc_out_be32(intc + IER, 0); /* Acknowledge any pending interrupts just in case. */ intc_out_be32(intc + IAR, ~(u32) 0); /* Turn on the Master Enable. */ intc_out_be32(intc + MER, 0x3UL); ppc_md.get_irq = xilinx_pic_get_irq; for (i = 0; i < NR_IRQS; ++i) { irq_desc[i].chip = &xilinx_intc; if (XPAR_INTC_0_KIND_OF_INTR & (0x00000001 << i)) irq_desc[i].status &= ~IRQ_LEVEL; else irq_desc[i].status |= IRQ_LEVEL; } }