void intel_early_me_status(void)
{
struct me_hfs hfs;
struct me_hfs2 hfs2;
pci_read_dword_ptr(&hfs, PCI_ME_HFS);
pci_read_dword_ptr(&hfs2, PCI_ME_HFS2);
intel_me_status(&hfs, &hfs2);
}
static void post_system_agent_init(struct udevice *dev, struct udevice *me_dev,
struct pei_data *pei_data)
{
uint16_t done;
/*
* Send ME init done for SandyBridge here. This is done inside the
* SystemAgent binary on IvyBridge
*/
dm_pci_read_config16(dev, PCI_DEVICE_ID, &done);
done &= BASE_REV_MASK;
if (BASE_REV_SNB == done)
intel_early_me_init_done(dev, me_dev, ME_INIT_STATUS_SUCCESS);
else
intel_me_status(me_dev);
/* If PCIe init is skipped, set the PEG clock gating */
if (!pei_data->pcie_init)
setbits_le32(MCHBAR_REG(0x7010), 1);
}
int dram_init(void)
{
struct pei_data _pei_data __aligned(8);
struct pei_data *pei_data = &_pei_data;
struct udevice *dev, *me_dev, *pch_dev;
struct chipset_power_state ps;
const void *spd_data;
int ret, size;
memset(pei_data, '\0', sizeof(struct pei_data));
/* Print ME state before MRC */
ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
if (ret)
return ret;
intel_me_status(me_dev);
/* Save ME HSIO version */
ret = uclass_first_device(UCLASS_PCH, &pch_dev);
if (ret)
return ret;
if (!pch_dev)
return -ENODEV;
power_state_get(pch_dev, &ps);
intel_me_hsio_version(me_dev, &ps.hsio_version, &ps.hsio_checksum);
broadwell_fill_pei_data(pei_data);
mainboard_fill_pei_data(pei_data);
ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
if (ret)
return ret;
if (!dev)
return -ENODEV;
size = 256;
ret = mrc_locate_spd(dev, size, &spd_data);
if (ret)
return ret;
memcpy(pei_data->spd_data[0][0], spd_data, size);
memcpy(pei_data->spd_data[1][0], spd_data, size);
ret = prepare_mrc_cache(pei_data);
if (ret)
debug("prepare_mrc_cache failed: %d\n", ret);
debug("PEI version %#x\n", pei_data->pei_version);
ret = mrc_common_init(dev, pei_data, true);
if (ret)
return ret;
debug("Memory init done\n");
ret = sdram_find(dev);
if (ret)
return ret;
gd->ram_size = gd->arch.meminfo.total_32bit_memory;
debug("RAM size %llx\n", (unsigned long long)gd->ram_size);
debug("MRC output data length %#x at %p\n", pei_data->data_to_save_size,
pei_data->data_to_save);
/* S3 resume: don't save scrambler seed or MRC data */
if (pei_data->boot_mode != SLEEP_STATE_S3) {
/*
* This will be copied to SDRAM in reserve_arch(), then written
* to SPI flash in mrccache_save()
*/
gd->arch.mrc_output = (char *)pei_data->data_to_save;
gd->arch.mrc_output_len = pei_data->data_to_save_size;
}
gd->arch.pei_meminfo = pei_data->meminfo;
return 0;
}
