int board_early_init_r(void)
{
#ifndef CONFIG_SDCARD
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_16M, 1);
set_tlb(1, flashbase + 0x1000000,
CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
#endif
return 0;
}
int board_early_init_r(void)
{
/* Initialize PCA9557 devices */
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
/*
* Remap NOR flash region to caching-inhibited
* so that flash can be erased/programmed properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
/* Invalidate existing TLB entry for NOR flash */
disable_tlb(0);
set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_256M, 1);
flash_cs_fixup();
return 0;
}
/*ARGSUSED*/
static void
sdt_disable(void *arg, dtrace_id_t id, void *parg)
{
#pragma unused(arg,id)
sdt_probe_t *sdp = parg;
struct modctl *ctl = sdp->sdp_ctl;
ctl->mod_nenabled--;
if (!ctl->mod_loaded || ctl->mod_loadcnt != sdp->sdp_loadcnt)
goto err;
while (sdp != NULL) {
(void)ml_nofault_copy( (vm_offset_t)&sdp->sdp_savedval, (vm_offset_t)sdp->sdp_patchpoint,
(vm_size_t)sizeof(sdp->sdp_savedval));
/*
* Make the patched instruction visible via a data + instruction
* cache flush on platforms that need it
*/
flush_dcache((vm_offset_t)sdp->sdp_patchpoint,(vm_size_t)sizeof(sdp->sdp_savedval), 0);
invalidate_icache((vm_offset_t)sdp->sdp_patchpoint,(vm_size_t)sizeof(sdp->sdp_savedval), 0);
sdp = sdp->sdp_next;
}
err:
;
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
set_liodns();
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals();
#endif
/* Disable remote I2C connection to qixis fpga */
QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
brd_mux_lane_to_slot();
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
return 0;
}
static int board_init_r(void)
{
const unsigned int flashbase = CFG_FLASH_BASE;
const u8 flash_esel = e500_find_tlb_idx((void *)flashbase, 1);
checkboard();
/* Map the whole boot flash */
fsl_set_lbc_br(0, BR_PHYS_ADDR(CFG_FLASH_BASE_PHYS) | BR_PS_16 | BR_V);
fsl_set_lbc_or(0, 0xff000ff7);
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash */
e500_disable_tlb(flash_esel);
/*
* Remap Boot flash region to caching-inhibited
* so that flash can be erased properly.
*/
e500_set_tlb(1, flashbase, CFG_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_16M, 1);
fsl_l2_cache_init();
return 0;
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
set_liodns();
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals();
#endif
return 0;
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
return 0;
}
/*ARGSUSED*/
static void
fbt_suspend(void *arg, dtrace_id_t id, void *parg)
{
#pragma unused(arg,id)
fbt_probe_t *fbt = parg;
struct modctl *ctl = NULL;
for (; fbt != NULL; fbt = fbt->fbtp_next) {
ctl = fbt->fbtp_ctl;
ASSERT(ctl->mod_nenabled > 0);
if (!ctl->mod_loaded || (ctl->mod_loadcnt != fbt->fbtp_loadcnt))
continue;
(void)ml_nofault_copy( (vm_offset_t)&fbt->fbtp_savedval, (vm_offset_t)fbt->fbtp_patchpoint,
sizeof(fbt->fbtp_savedval));
/*
* Make the patched instruction visible via a data + instruction
* cache flush for the platforms that need it
*/
flush_dcache((vm_offset_t)fbt->fbtp_patchpoint,(vm_size_t)sizeof(fbt->fbtp_savedval), 0);
invalidate_icache((vm_offset_t)fbt->fbtp_patchpoint,(vm_size_t)sizeof(fbt->fbtp_savedval), 0);
fbt->fbtp_currentval = fbt->fbtp_savedval;
}
dtrace_membar_consumer();
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
set_liodns();
setup_portals();
return 0;
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
unsigned int orig_bus = i2c_get_bus_num();
u8 i2c_data;
i2c_set_bus_num(1);
if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0,
1, &i2c_data, sizeof(i2c_data)) == 0) {
if (i2c_data & 0x2)
puts("NOR Flash Bank : Secondary\n");
else
puts("NOR Flash Bank : Primary\n");
if (i2c_data & 0x1) {
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
puts("SD/MMC : 8-bit Mode\n");
puts("eSPI : Disabled\n");
} else {
puts("SD/MMC : 4-bit Mode\n");
puts("eSPI : Enabled\n");
}
} else {
puts("Failed reading I2C Chip 0x18 on bus 1\n");
}
i2c_set_bus_num(orig_bus);
/*
* Remap Boot flash region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_16M, 1);
rtc_reset();
return 0;
}
void arch_livepatch_revive(void)
{
/*
* Nuke the instruction cache. Data cache has been cleaned before in
* arch_livepatch_[apply|revert].
*/
invalidate_icache();
if ( vmap_of_xen_text )
vunmap(vmap_of_xen_text);
vmap_of_xen_text = NULL;
}
int board_early_init_r(void)
{
int ret = 0;
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
set_liodns();
setup_portals();
ret = trigger_fpga_config();
if (ret)
printf("error triggering PCIe FPGA config\n");
return ret;
}
void flush_page_to_ram(unsigned long mfn)
{
void *v = map_domain_page(_mfn(mfn));
clean_and_invalidate_dcache_va_range(v, PAGE_SIZE);
unmap_domain_page(v);
/*
* For some of the instruction cache (such as VIPT), the entire I-Cache
* needs to be flushed to guarantee that all the aliases of a given
* physical address will be removed from the cache.
* Invalidating the I-Cache by VA highly depends on the behavior of the
* I-Cache (See D4.9.2 in ARM DDI 0487A.k_iss10775). Instead of using flush
* by VA on select platforms, we just flush the entire cache here.
*/
invalidate_icache();
}
static int
invalidate_core_icache(struct pcx_pkt *pcx_pkt, int core_id, int target_core_id, taddr_opt_t t1_addr)
{
int way, pabit5;
struct cpx_pkt cpx_pkt_buf;
struct cpx_pkt *cpx_pkt = &cpx_pkt_buf;
way = invalidate_icache(target_core_id, t1_addr);
if (way == -1) {
return way;
}
CPX_PKT_CTRL_EVICT_INV(cpx_pkt, 0);
cpx_pkt->data3 = 0;
cpx_pkt->data2 = 0;
cpx_pkt->data1 = 0;
cpx_pkt->data0 = 0;
pabit5 = (t1_addr & 0x20) >> 5;
switch (pabit5) {
case 0:
cpx_pkt->data0 |= (way << 2);
cpx_pkt->data0 |= 0x2;
cpx_pkt->data0 <<= (target_core_id * 4);
break;
case 1:
cpx_pkt->data1 |= (way << 2);
cpx_pkt->data1 |= 0x2;
cpx_pkt->data1 <<= 24;
cpx_pkt->data1 <<= (target_core_id * 4);
break;
}
CPX_PKT_REFLECT_THREAD_ID(cpx_pkt, pcx_pkt);
CPX_PKT_REFLECT_BIS(cpx_pkt, pcx_pkt);
CPX_PKT_REFLECT_ADDR_5_4(cpx_pkt, pcx_pkt);
CPX_PKT_REFLECT_ADDR_11_6(cpx_pkt, pcx_pkt);
CPX_PKT_REFLECT_CORE_ID(cpx_pkt, pcx_pkt);
send_cpx_pkt(target_core_id, cpx_pkt);
return way;
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
/* Disable remote I2C connection to qixis fpga */
QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
/*
* Adjust core voltage according to voltage ID
* This function changes I2C mux to channel 2.
*/
if (adjust_vdd(0))
printf("Warning: Adjusting core voltage failed.\n");
brd_mux_lane_to_slot();
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
return 0;
}
void
return_load_req(struct pcx_pkt *pcx_pkt,
struct cpx_pkt *cpx_pkt,
taddr_opt_t t1_addr,
maddr_t mb_addr,
uint32_t preinit_ctrl_flag)
{
int way;
maddr_t mb_addr_qw_align;
int core_id;
core_id = PCX_PKT_GET_CORE_ID(pcx_pkt);
if (mb_addr != MB_INVALID_ADDR) {
mb_addr_qw_align = mb_addr & MB_ADDR_QWORD_ALIGN_MASK;
cpx_pkt->data3 = *(uint32_t *) (mb_addr_qw_align + 0x0);
cpx_pkt->data2 = *(uint32_t *) (mb_addr_qw_align + 0x4);
cpx_pkt->data1 = *(uint32_t *) (mb_addr_qw_align + 0x8);
cpx_pkt->data0 = *(uint32_t *) (mb_addr_qw_align + 0xC);
}
CPX_PKT_CTRL_LOAD(cpx_pkt, preinit_ctrl_flag);
CPX_PKT_REFLECT_NC_THREAD_ID(cpx_pkt, pcx_pkt);
CPX_PKT_REFLECT_PREFETCH(cpx_pkt, pcx_pkt);
if (PCX_PKT_IS_CACHEABLE(pcx_pkt)) {
invalidate_other_icache(pcx_pkt, t1_addr);
way = invalidate_icache(core_id, t1_addr);
if (way != -1) {
CPX_PKT_SET_WV(cpx_pkt, 1);
CPX_PKT_SET_WAY(cpx_pkt, way);
}
}
send_cpx_pkt(core_id, cpx_pkt);
return;
}
/*ARGSUSED*/
static void
fbt_resume(void *arg, dtrace_id_t id, void *parg)
{
#pragma unused(arg,id)
fbt_probe_t *fbt = parg;
struct modctl *ctl = NULL;
for (; fbt != NULL; fbt = fbt->fbtp_next) {
ctl = fbt->fbtp_ctl;
ASSERT(ctl->mod_nenabled > 0);
if (!ctl->mod_loaded || (ctl->mod_loadcnt != fbt->fbtp_loadcnt))
continue;
dtrace_casptr(&tempDTraceTrapHook, NULL, fbt_perfCallback);
if (tempDTraceTrapHook != (perfCallback)fbt_perfCallback) {
if (fbt_verbose) {
cmn_err(CE_NOTE, "fbt_resume is failing for probe %s "
"in module %s: tempDTraceTrapHook already occupied.",
fbt->fbtp_name, ctl->mod_modname);
}
return;
}
(void)ml_nofault_copy( (vm_offset_t)&fbt->fbtp_patchval, (vm_offset_t)fbt->fbtp_patchpoint,
sizeof(fbt->fbtp_patchval));
#if CONFIG_EMBEDDED
/*
* Make the patched instruction visible via a data + instruction cache flush.
*/
flush_dcache((vm_offset_t)fbt->fbtp_patchpoint,(vm_size_t)sizeof(fbt->fbtp_patchval), 0);
invalidate_icache((vm_offset_t)fbt->fbtp_patchpoint,(vm_size_t)sizeof(fbt->fbtp_patchval), 0);
#endif
fbt->fbtp_currentval = fbt->fbtp_patchval;
}
dtrace_membar_consumer();
}
static void process_load_fast(struct pcx_pkt *pcx_pkt, struct cpx_pkt *cpx_pkt) {
uint_t l1_way;
int signed_way;
int core_id;
taddr_opt_t t1_addr;
maddr_t mb_addr, mb_addr_qw_align;
core_id = PCX_PKT_GET_CORE_ID(pcx_pkt);
t1_addr = PCX_PKT_GET_T1_ADDR_OPT(pcx_pkt);
mb_addr = t1_addr_to_max(t1_addr);
l1_way = PCX_PKT_GET_L1_WAY(pcx_pkt);
add_dcache_line(core_id, t1_addr, l1_way);
CPX_PKT_CTRL_LOAD(cpx_pkt, 0);
mb_addr_qw_align = mb_addr & MB_ADDR_QWORD_ALIGN_MASK;
cpx_pkt->data3 = *(uint32_t *) (mb_addr_qw_align + 0x0);
cpx_pkt->data2 = *(uint32_t *) (mb_addr_qw_align + 0x4);
cpx_pkt->data1 = *(uint32_t *) (mb_addr_qw_align + 0x8);
cpx_pkt->data0 = *(uint32_t *) (mb_addr_qw_align + 0xC);
CPX_PKT_REFLECT_THREAD_ID(cpx_pkt, pcx_pkt);
invalidate_other_icache(pcx_pkt, t1_addr);
signed_way = invalidate_icache(core_id, t1_addr);
if (signed_way != -1) {
CPX_PKT_SET_WV(cpx_pkt, 1);
CPX_PKT_SET_WAY(cpx_pkt, signed_way);
}
//send_cpx_pkt(core_id, cpx_pkt);
return;
}
int board_early_init_r(void)
{
int ret = 0;
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
set_liodns();
setup_qbman_portals();
ret = trigger_fpga_config();
if (ret)
printf("error triggering PCIe FPGA config\n");
/* enable the Unit LED (red) & Boot LED (on) */
qrio_set_leds();
/* enable Application Buffer */
qrio_enable_app_buffer();
return ret;
}
int codec_load_ram(char* codecptr, int size, void* ptr2, int bufwrap,
struct codec_api *api)
{
enum codec_status (*codec_start)(const struct codec_api* api);
int status;
#ifndef SIMULATOR
int copy_n;
if ((char *)&codecbuf[0] != codecptr) {
/* zero out codec buffer to ensure a properly zeroed bss area */
memset(codecbuf, 0, CODEC_SIZE);
size = MIN(size, CODEC_SIZE);
copy_n = MIN(size, bufwrap);
memcpy(codecbuf, codecptr, copy_n);
size -= copy_n;
if (size > 0) {
memcpy(&codecbuf[copy_n], ptr2, size);
}
}
codec_start = (void*)&codecbuf;
#else /* SIMULATOR */
int pd;
codec_start = sim_codec_load_ram(codecptr, size, ptr2, bufwrap, &pd);
if (pd < 0)
return CODEC_ERROR;
#endif /* SIMULATOR */
invalidate_icache();
status = codec_start(api);
#ifdef SIMULATOR
sim_codec_close(pd);
#endif
return status;
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
const u8 flash_esel = 0;
/*
* Remap Boot flash to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
0, flash_esel, /* ts, esel */
BOOKE_PAGESZ_64M, 1); /* tsize, iprot */
return 0;
}
static int p1010rdb_board_init_r(void)
{
const uint32_t flashbase = CFG_BOOT_BLOCK;
const u8 flash_esel = e500_find_tlb_idx((void *)flashbase, 1);
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash */
e500_disable_tlb(flash_esel);
/*
* Remap Boot flash region to caching-inhibited
* so that flash can be erased properly.
*/
e500_set_tlb(1, flashbase, CFG_BOOT_BLOCK_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
fsl_l2_cache_init();
return 0;
}
long xexec(WORD flag, char *path, char *tail, char *env)
{
PD *p;
PGMHDR01 hdr;
MD *m, *env_md;
LONG rc;
long max, needed;
FH fh;
D(("BDOS: xexec - flag or mode = %d\n", flag));
/* first branch - actions that do not require loading files */
switch(flag) {
case PE_RELOCATE:
p = (PD *) tail;
rc = kpgm_relocate(p, (long)path);
if(rc) {
D(("BDOS: xexec - kpgm_relloc returned %ld (0x%lx)\n", rc, rc));
return(rc);
}
/* invalidate instruction cache for the TEXT segment only
* programs that jump into their DATA, BSS or HEAP are kindly invited
* to do their cache management themselves.
*/
invalidate_icache( p+1, p->p_tlen);
return (long) p;
case PE_BASEPAGE:
/* just create a basepage */
env_md = alloc_env(env);
if(env_md == NULL) {
D(("xexec: Not Enough Memory!\n"));
return(ENSMEM);
}
max = (long) ffit(-1L, &pmd);
if(max >= sizeof(PD)) {
m = ffit(max, &pmd);
p = (PD *) m->m_start;
} else {
/* not even enough memory for basepage */
freeit(env_md, &pmd);
D(("xexec: No memory for TPA\n"));
return(ENSMEM);
}
/* memory ownership */
m->m_own = env_md->m_own = run;
/* initialize the PD */
init_pd_fields(p, tail, max, env_md);
init_pd_files(p);
return (long) p;
case PE_GOTHENFREE:
/* set the owner of the memory to be this process */
p = (PD *) tail;
set_owner(p, p, find_mpb(p));
set_owner(p->p_env, p, find_mpb(p->p_env));
/* fall through */
case PE_GO:
p = (PD *) tail;
proc_go(p);
/* should not return ? */
return (long)p;
case PE_LOADGO:
case PE_LOAD:
break;
default:
return EINVFN;
}
/* we now need to load a file */
D(("BDOS: xexec - trying to find the command ...\n"));
if (ixsfirst(path,0,0L)) {
D(("BDOS: Command %s not found!!!\n", path));
return(EFILNF); /* file not found */
}
/* load the header - if IO error occurs now, the longjmp in rwabs will
* jump directly back to bdosmain.c, which is not a problem because
* we haven't allocated anything yet.
*/
rc = kpgmhdrld(path, &hdr, &fh);
if(rc) {
D(("BDOS: xexec - kpgmhdrld returned %ld (0x%lx)\n", rc, rc));
return(rc);
}
/* allocate the environment first, always in ST RAM */
env_md = alloc_env(env);
if ( env_md == NULL ) {
D(("xexec: Not Enough Memory!\n"));
return(ENSMEM);
}
/* allocate the basepage depending on memory policy */
needed = hdr.h01_tlen + hdr.h01_dlen + hdr.h01_blen + sizeof(PD);
max = 0;
/* first try */
p = NULL;
m = NULL;
#if CONF_WITH_ALT_RAM
if(has_alt_ram && (hdr.h01_flags & PF_TTRAMLOAD)) {
/* use alternate ram preferably */
max = (long) ffit(-1L, &pmdalt);
if(max >= needed) {
m = ffit(max, &pmdalt);
p = (PD *) m->m_start;
}
}
#endif
/* second try */
if(p == NULL) {
max = (long) ffit(-1L, &pmd);
if(max >= needed) {
m = ffit(max, &pmd);
p = (PD *) m->m_start;
}
}
/* still failed? free env_md and return */
if(p == NULL) {
D(("xexec: No memory for TPA\n"));
freeit(env_md, &pmd);
return(ENSMEM);
}
assert(m != NULL);
/* memory ownership - the owner is either the new process being created,
* or the parent
*/
if(flag == PE_LOADGO) {
m->m_own = env_md->m_own = p;
} else {
m->m_own = env_md->m_own = run;
}
/* initialize the fields in the PD structure */
init_pd_fields(p, tail, max, env_md);
/* set the flags (must be done after init_pd) */
p->p_flags = hdr.h01_flags;
/* use static variable to avoid the obscure longjmp warning */
cur_p = p;
cur_m = m;
cur_env_md = env_md;
/* we have now allocated memory, so we need to intercept longjmp. */
memcpy(bakbuf, errbuf, sizeof(errbuf));
if ( setjmp(errbuf) ) {
kprintf("Error and longjmp in xexec()!\n");
/* free any memory allocated yet */
freeit(cur_env_md, &pmd);
freeit(cur_m, find_mpb((void *)cur_m->m_start));
/* we still have to jump back to bdosmain.c so that the proper error
* handling can occur.
*/
longjmp(bakbuf, 1);
}
/* now, load the rest of the program and perform relocation */
rc = kpgmld(cur_p, fh, &hdr);
if ( rc ) {
D(("BDOS: xexec - kpgmld returned %ld (0x%lx)\n", rc, rc));
/* free any memory allocated yet */
freeit(cur_env_md, &pmd);
freeit(cur_m, find_mpb((void *)cur_m->m_start));
return rc;
}
/* at this point the program has been correctly loaded in memory, and
* more IO errors cannot occur, so it is safe now to finish initializing
* the new process.
*/
init_pd_files(cur_p);
/* invalidate instruction cache for the TEXT segment only
* programs that jump into their DATA, BSS or HEAP are kindly invited
* to do their cache management themselves.
*/
invalidate_icache(((char *)cur_p) + sizeof(PD), hdr.h01_tlen);
if(flag != PE_LOAD)
proc_go(cur_p);
return (long) cur_p;
}
int sys_execve(const char *filename, char *const argv[], char *const envp[]){
__UNUSED_VARIABLE(envp);
int ret;
unsigned int sp;
unsigned int *tmp_sp;
char *tmp_argv[6];
unsigned int argv_pos;
int argc, i, len;
int stack_end;
ret = elf_load(filename);
if(ret < 0)
return ret;
stack_end = ret;
Task *prev_task = Kernel::getInstance()->taskmanager.getCurrentTask();
Task *current = Kernel::getInstance()->taskmanager.getTask();
if(current == NULL){
lcd_printf("Task Allocation Error\n");
for(;;);
}
sp = 0x80000; // max memory size
argc = 0;
while(argv[argc] != 0)
argc++;
for(i = 0; i < argc; i++){
len = strlen(argv[i]) + 1;
sp -= len;
sp &= 0xfffffff0; //16 byte alignment
tmp_argv[i] = (char *)sp;
memcpy((void *)sp, argv[i], len);
}
sp -= 4 * (argc + 1); // num of argv and argv[argc]
argv_pos = sp;
tmp_sp = (unsigned int *)sp;
for(i = 0; i < argc; i++){
*tmp_sp = (unsigned int)tmp_argv[i];
tmp_sp++;
}
*tmp_sp = 0;
sp -= 4*3; // argc, argv, envp
tmp_sp = (unsigned int *)sp;
*tmp_sp++ = argc;
*tmp_sp++ = argv_pos; //argv
*tmp_sp = 0; //envp
current->tss.sp = sp;
current->tss.ra = 0x20000;
current->tss.cp0_status = 0;
current->tss.cp0_epc = 0;
current->tss.cp0_cause = 0;
current->stack_start = sp;
current->stack_end = stack_end;
current->brk = stack_end;
invalidate_icache();
invalidate_dcache();
Kernel::getInstance()->taskmanager.switchContext(prev_task, current);
return 0;
}
/*ARGSUSED*/
static int
sdt_enable(void *arg, dtrace_id_t id, void *parg)
{
#pragma unused(arg,id)
sdt_probe_t *sdp = parg;
struct modctl *ctl = sdp->sdp_ctl;
ctl->mod_nenabled++;
/*
* If this module has disappeared since we discovered its probes,
* refuse to enable it.
*/
if (!ctl->mod_loaded) {
if (sdt_verbose) {
cmn_err(CE_NOTE, "sdt is failing for probe %s "
"(module %s unloaded)",
sdp->sdp_name, ctl->mod_modname);
}
goto err;
}
/*
* Now check that our modctl has the expected load count. If it
* doesn't, this module must have been unloaded and reloaded -- and
* we're not going to touch it.
*/
if (ctl->mod_loadcnt != sdp->sdp_loadcnt) {
if (sdt_verbose) {
cmn_err(CE_NOTE, "sdt is failing for probe %s "
"(module %s reloaded)",
sdp->sdp_name, ctl->mod_modname);
}
goto err;
}
dtrace_casptr(&tempDTraceTrapHook, NULL, fbt_perfCallback);
if (tempDTraceTrapHook != (perfCallback)fbt_perfCallback) {
if (sdt_verbose) {
cmn_err(CE_NOTE, "sdt_enable is failing for probe %s "
"in module %s: tempDTraceTrapHook already occupied.",
sdp->sdp_name, ctl->mod_modname);
}
return (0);
}
while (sdp != NULL) {
(void)ml_nofault_copy( (vm_offset_t)&sdp->sdp_patchval, (vm_offset_t)sdp->sdp_patchpoint,
(vm_size_t)sizeof(sdp->sdp_patchval));
/*
* Make the patched instruction visible via a data + instruction
* cache fush on platforms that need it
*/
flush_dcache((vm_offset_t)sdp->sdp_patchpoint,(vm_size_t)sizeof(sdp->sdp_patchval), 0);
invalidate_icache((vm_offset_t)sdp->sdp_patchpoint,(vm_size_t)sizeof(sdp->sdp_patchval), 0);
sdp = sdp->sdp_next;
}
err:
return (0);
}
static int da923rc_board_init_r(void)
{
void __iomem *lbc = LBC_BASE_ADDR;
void __iomem *ecm = IOMEM(MPC85xx_ECM_ADDR);
void __iomem *pci = IOMEM(PCI1_BASE_ADDR);
const unsigned int flashbase = (BOOT_BLOCK + 0x2000000);
uint8_t flash_esel;
da923rc_boardinfo_get(&binfo);
flush_dcache();
invalidate_icache();
/* Clear LBC error interrupts */
out_be32(lbc + FSL_LBC_LTESR_OFFSET, 0xffffffff);
/* Enable LBC error interrupts */
out_be32(lbc + FSL_LBC_LTEIR_OFFSET, 0xffffffff);
/* Clear ecm errors */
out_be32(ecm + MPC85xx_ECM_EEDR_OFFSET, 0xffffffff);
/* Enable ecm errors */
out_be32(ecm + MPC85xx_ECM_EEER_OFFSET, 0xffffffff);
/* Re-map boot flash */
fsl_set_lbc_br(0, BR_PHYS_ADDR(0xfe000000) | BR_PS_16 | BR_V);
fsl_set_lbc_or(0, 0xfe006e21);
/* Invalidate TLB entry for boot block */
flash_esel = e500_find_tlb_idx((void *)flashbase, 1);
e500_disable_tlb(flash_esel);
flash_esel = e500_find_tlb_idx((void *)(flashbase + 0x1000000), 1);
e500_disable_tlb(flash_esel);
/* Boot block back to cache inhibited. */
e500_set_tlb(1, BOOT_BLOCK + (2 * 0x1000000),
BOOT_BLOCK + (2 * 0x1000000),
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G | MAS2_M,
0, 2, BOOKE_PAGESZ_16M, 1);
e500_set_tlb(1, BOOT_BLOCK + (3 * 0x1000000),
BOOT_BLOCK + (3 * 0x1000000),
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G | MAS2_M,
0, 3, BOOKE_PAGESZ_16M, 1);
fsl_l2_cache_init();
fsl_enable_gpiout();
/* Enable NOR low voltage programming (gpio 2) and write (gpio 3). */
gpio_set_value(2, 1);
gpio_set_value(3, 1);
/* Enable write to NAND flash */
if (binfo.bid == BOARD_TYPE_GBX460) {
/* Map CPLD */
fsl_set_lbc_br(3, BR_PHYS_ADDR(0xfc010000) | BR_PS_16 | BR_V);
fsl_set_lbc_or(3, 0xffffe001);
/* Enable all reset */
out_be16(IOMEM(0xfc010044), 0xffff);
gpio_set_value(6, 1);
}
/* Board reset and PHY reset. Disable CS3. */
if (binfo.bid == BOARD_TYPE_DA923) {
gpio_set_value(0, 0);
gpio_set_value(1, 1);
/* De-assert Board reset */
udelay(1000);
gpio_set_value(0, 1);
}
/* Enable PCI error reporting */
out_be32(pci + 0xe00, 0x80000040);
out_be32(pci + 0xe08, 0x6bf);
out_be32(pci + 0xe0c, 0xbb1fa001);
/* 32-bytes cacheline size */
out_be32(pci, 0x8000000c);
out_le32(pci + 4, 0x00008008);
return 0;
}
void __flush_icache_range(unsigned long start, unsigned long end)
{
invalidate_icache((const void *)start, end - start, PAGE_SIZE);
}
/*ARGSUSED*/
int
fbt_enable(void *arg, dtrace_id_t id, void *parg)
{
#pragma unused(arg,id)
fbt_probe_t *fbt = parg;
struct modctl *ctl = NULL;
for (; fbt != NULL; fbt = fbt->fbtp_next) {
ctl = fbt->fbtp_ctl;
if (!ctl->mod_loaded) {
if (fbt_verbose) {
cmn_err(CE_NOTE, "fbt is failing for probe %s "
"(module %s unloaded)",
fbt->fbtp_name, ctl->mod_modname);
}
continue;
}
/*
* Now check that our modctl has the expected load count. If it
* doesn't, this module must have been unloaded and reloaded -- and
* we're not going to touch it.
*/
if (ctl->mod_loadcnt != fbt->fbtp_loadcnt) {
if (fbt_verbose) {
cmn_err(CE_NOTE, "fbt is failing for probe %s "
"(module %s reloaded)",
fbt->fbtp_name, ctl->mod_modname);
}
continue;
}
dtrace_casptr(&tempDTraceTrapHook, NULL, fbt_perfCallback);
if (tempDTraceTrapHook != (perfCallback)fbt_perfCallback) {
if (fbt_verbose) {
cmn_err(CE_NOTE, "fbt_enable is failing for probe %s "
"in module %s: tempDTraceTrapHook already occupied.",
fbt->fbtp_name, ctl->mod_modname);
}
continue;
}
if (fbt->fbtp_currentval != fbt->fbtp_patchval) {
(void)ml_nofault_copy( (vm_offset_t)&fbt->fbtp_patchval, (vm_offset_t)fbt->fbtp_patchpoint,
sizeof(fbt->fbtp_patchval));
/*
* Make the patched instruction visible via a data + instruction
* cache flush for the platforms that need it
*/
flush_dcache((vm_offset_t)fbt->fbtp_patchpoint,(vm_size_t)sizeof(fbt->fbtp_patchval), 0);
invalidate_icache((vm_offset_t)fbt->fbtp_patchpoint,(vm_size_t)sizeof(fbt->fbtp_patchval), 0);
fbt->fbtp_currentval = fbt->fbtp_patchval;
ctl->mod_nenabled++;
}
}
dtrace_membar_consumer();
return (0);
}
