static void __init
ocotea_setup_arch(void)
{
unsigned char *addr;
unsigned long long mac64;
bd_t *bip = (bd_t *) __res;
/* Retrieve MAC addresses from flash */
addr = ioremap64(OCOTEA_MAC_BASE, OCOTEA_MAC_SIZE);
mac64 = simple_strtoull(addr, 0, 16);
memcpy(bip->bi_enetaddr[0], (char *)&mac64+2, 6);
mac64 = simple_strtoull(addr+OCOTEA_MAC1_OFFSET, 0, 16);
memcpy(bip->bi_enetaddr[1], (char *)&mac64+2, 6);
iounmap(addr);
/* Set EMAC PHY map to not probe address 0x00 */
emac_phy_map[0] = 0x00000001;
emac_phy_map[1] = 0x00000001;
#if !defined(CONFIG_BDI_SWITCH)
/*
* The Abatron BDI JTAG debugger does not tolerate others
* mucking with the debug registers.
*/
mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
#endif
/* Setup TODC access */
TODC_INIT(TODC_TYPE_DS1743,
0,
0,
ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE),
8);
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Setup PCI host bridge */
ocotea_setup_hose();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = to_kdev_t(0x0100); /* /dev/ram */
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = to_kdev_t(0x00ff); /* /dev/nfs */
#else
ROOT_DEV = to_kdev_t(0x0301); /* /dev/hda1 */
#endif
#ifdef CONFIG_VT
conswitchp = &dummy_con;
#endif
ocotea_early_serial_map();
/* Identify the system */
printk("IBM Ocotea port (MontaVista Software, Inc. <*****@*****.**>)\n");
}
static void __init
ebony_setup_arch(void)
{
unsigned char * vpd_base;
struct ocp_def *def;
struct ocp_func_emac_data *emacdata;
/* Set mac_addr for each EMAC */
vpd_base = ioremap64(EBONY_VPD_BASE, EBONY_VPD_SIZE);
def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
emacdata = def->additions;
memcpy(emacdata->mac_addr, EBONY_NA0_ADDR(vpd_base), 6);
def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
emacdata = def->additions;
memcpy(emacdata->mac_addr, EBONY_NA1_ADDR(vpd_base), 6);
iounmap(vpd_base);
/*
* Determine various clocks.
* To be completely correct we should get SysClk
* from FPGA, because it can be changed by on-board switches
* --ebs
*/
ibm440gp_get_clocks(&clocks, 33333333, 6 * 1843200);
ocp_sys_info.opb_bus_freq = clocks.opb;
/* Setup TODC access */
TODC_INIT(TODC_TYPE_DS1743,
0,
0,
ioremap64(EBONY_RTC_ADDR, EBONY_RTC_SIZE),
8);
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Setup PCI host bridge */
ebony_setup_hose();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA1;
#endif
ebony_early_serial_map();
/* Identify the system */
printk("IBM Ebony port (MontaVista Software, Inc. ([email protected]))\n");
}
static void __init
ebony_early_serial_map(void)
{
struct uart_port port;
/* Setup ioremapped serial port access */
memset(&port, 0, sizeof(port));
port.membase = ioremap64(PPC440GP_UART0_ADDR, 8);
port.irq = 0;
port.uartclk = clocks.uart0;
port.regshift = 0;
port.iotype = SERIAL_IO_MEM;
port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
port.line = 0;
#ifdef CONFIG_SERIAL_8250
if (early_serial_setup(&port) != 0)
printk("Early serial init of port 0 failed\n");
#endif
#ifdef CONFIG_SERIAL_TEXT_DEBUG
/* Configure debug serial access */
gen550_init(0, &port);
#endif
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(0, &port);
#endif
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_8250)
/* Purge TLB entry added in head_44x.S for early serial access */
_tlbie(UART0_IO_BASE);
#endif
port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
port.irq = 1;
port.uartclk = clocks.uart1;
port.line = 1;
#ifdef CONFIG_SERIAL_8250
if (early_serial_setup(&port) != 1)
printk("Early serial init of port 1 failed\n");
#endif
#ifdef CONFIG_SERIAL_TEXT_DEBUG
/* Configure debug serial access */
gen550_init(1, &port);
#endif
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(1, &port);
#endif
}
static void __init
luan_early_serial_map(void)
{
struct uart_port port;
/* Setup ioremapped serial port access */
memset(&port, 0, sizeof(port));
port.membase = ioremap64(PPC440SP_UART0_ADDR, 8);
port.irq = UART0_INT;
port.uartclk = clocks.uart0;
port.regshift = 0;
port.iotype = SERIAL_IO_MEM;
port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
port.line = 0;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 0 failed\n");
}
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(0, &port);
#endif
port.membase = ioremap64(PPC440SP_UART1_ADDR, 8);
port.irq = UART1_INT;
port.uartclk = clocks.uart1;
port.line = 1;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 1 failed\n");
}
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(1, &port);
#endif
/* Enable UART2 */
SDR_WRITE(DCRN_SDR_PFC1, SDR_READ(DCRN_SDR_PFC1) | 0x01000000);
port.membase = ioremap64(PPC440SP_UART2_ADDR, 8);
port.irq = UART2_INT;
port.uartclk = clocks.uart2;
port.line = 2;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 2 failed\n");
}
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(2, &port);
#endif
}
static void __init
yosemite_setup_hose(void)
{
unsigned int bar_response, bar;
struct pci_controller *hose;
yosemite_setup_pci();
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = YOSEMITE_PCI_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
YOSEMITE_PCI_LOWER_IO,
YOSEMITE_PCI_UPPER_IO,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
YOSEMITE_PCI_LOWER_MEM,
YOSEMITE_PCI_UPPER_MEM,
IORESOURCE_MEM,
"PCI host bridge");
ppc_md.pci_exclude_device = yosemite_exclude_device;
hose->io_space.start = YOSEMITE_PCI_LOWER_IO;
hose->io_space.end = YOSEMITE_PCI_UPPER_IO;
hose->mem_space.start = YOSEMITE_PCI_LOWER_MEM;
hose->mem_space.end = YOSEMITE_PCI_UPPER_MEM;
isa_io_base =
(unsigned long)ioremap64(YOSEMITE_PCI_IO_BASE, YOSEMITE_PCI_IO_SIZE);
hose->io_base_virt = (void *)isa_io_base;
setup_indirect_pci(hose,
YOSEMITE_PCI_CFGA_PLB32,
YOSEMITE_PCI_CFGD_PLB32);
hose->set_cfg_type = 1;
/* Zero config bars */
for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
early_write_config_dword(hose, hose->first_busno,
PCI_FUNC(hose->first_busno), bar,
0x00000000);
early_read_config_dword(hose, hose->first_busno,
PCI_FUNC(hose->first_busno), bar,
&bar_response);
}
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = yosemite_map_irq;
}
void *
ioremap(phys_addr_t addr, unsigned long size)
{
phys_addr_t addr64 = fixup_bigphys_addr(addr, size);;
return ioremap64(addr64, size);
}
static int ndfc_nand_probe(struct platform_device *pdev)
{
struct platform_nand_ctrl *nc = pdev->dev.platform_data;
struct ndfc_controller_settings *settings = nc->priv;
struct resource *res = pdev->resource;
struct ndfc_controller *ndfc = &ndfc_ctrl;
unsigned long long phys = ((unsigned long long)settings->ndfc_erpn << 32)
| res->start;
ndfc->ndfcbase = ioremap64(phys, res->end - res->start + 1);
if (!ndfc->ndfcbase) {
printk(KERN_ERR "NDFC: ioremap failed\n");
return -EIO;
}
__raw_writel(settings->ccr_settings, ndfc->ndfcbase + NDFC_CCR);
spin_lock_init(&ndfc->ndfc_control.lock);
init_waitqueue_head(&ndfc->ndfc_control.wq);
platform_set_drvdata(pdev, ndfc);
printk("NDFC NAND Driver initialized. Chip-Rev: 0x%08x\n",
__raw_readl(ndfc->ndfcbase + NDFC_REVID));
return 0;
}
/*
* FIXME: This is only here to "make it work". This will move
* to a ibm_pcix.c which will contain a generic IBM PCIX bridge
* configuration library. -Matt
*/
static void __init
ebony_setup_pcix(void)
{
void *pcix_reg_base;
pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
/* Disable all windows */
PCIX_WRITEL(0, PCIX0_POM0SA);
PCIX_WRITEL(0, PCIX0_POM1SA);
PCIX_WRITEL(0, PCIX0_POM2SA);
PCIX_WRITEL(0, PCIX0_PIM0SA);
PCIX_WRITEL(0, PCIX0_PIM1SA);
PCIX_WRITEL(0, PCIX0_PIM2SA);
/* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
/* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
eieio();
}
/*
* FIXME: This is only here to "make it work". This will move
* to a ibm_pcix.c which will contain a generic IBM PCIX bridge
* configuration library. -Matt
*/
static void __init
ocotea_setup_pcix(void)
{
void *pcix_reg_base;
pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
/* Enable PCIX0 I/O, Mem, and Busmaster cycles */
PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
/* Disable all windows */
PCIX_WRITEL(0, PCIX0_POM0SA);
PCIX_WRITEL(0, PCIX0_POM1SA);
PCIX_WRITEL(0, PCIX0_POM2SA);
PCIX_WRITEL(0, PCIX0_PIM0SA);
PCIX_WRITEL(0, PCIX0_PIM0SAH);
PCIX_WRITEL(0, PCIX0_PIM1SA);
PCIX_WRITEL(0, PCIX0_PIM2SA);
PCIX_WRITEL(0, PCIX0_PIM2SAH);
/* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
/* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA);
eieio();
}
/*
* For the given slot, set rootpoint mode, send power to the slot,
* turn on the green LED and turn off the yellow LED, enable the clock
* and turn off reset.
*/
static void __init yucca_setup_pcie_fpga_rootpoint(int port)
{
void __iomem *pcie_reg_fpga_base;
u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
pcie_reg_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE);
switch(port) {
case 0:
rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
endpoint = 0;
power = FPGA_REG1A_PE0_PWRON;
green_led = FPGA_REG1A_PE0_GLED;
clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
yellow_led = FPGA_REG1A_PE0_YLED;
reset_off = FPGA_REG1C_PE0_PERST;
break;
case 1:
rootpoint = 0;
endpoint = FPGA_REG1C_PE1_ENDPOINT;
power = FPGA_REG1A_PE1_PWRON;
green_led = FPGA_REG1A_PE1_GLED;
clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
yellow_led = FPGA_REG1A_PE1_YLED;
reset_off = FPGA_REG1C_PE1_PERST;
break;
case 2:
rootpoint = 0;
endpoint = FPGA_REG1C_PE2_ENDPOINT;
power = FPGA_REG1A_PE2_PWRON;
green_led = FPGA_REG1A_PE2_GLED;
clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
yellow_led = FPGA_REG1A_PE2_YLED;
reset_off = FPGA_REG1C_PE2_PERST;
break;
default:
iounmap(pcie_reg_fpga_base);
return;
}
out_be16(pcie_reg_fpga_base + FPGA_REG1A,
~(power | clock | green_led) &
(yellow_led | in_be16(pcie_reg_fpga_base + FPGA_REG1A)));
out_be16(pcie_reg_fpga_base + FPGA_REG1C,
~(endpoint | reset_off) &
(rootpoint | in_be16(pcie_reg_fpga_base + FPGA_REG1C)));
/*
* Leave device in reset for a while after powering on the
* slot to give it a chance to initialize.
*/
mdelay(250);
out_be16(pcie_reg_fpga_base + FPGA_REG1C,
reset_off | in_be16(pcie_reg_fpga_base + FPGA_REG1C));
iounmap(pcie_reg_fpga_base);
}
static void __init
yosemite_early_serial_map(void)
{
struct uart_port port;
/* Setup ioremapped serial port access */
memset(&port, 0, sizeof(port));
port.mapbase = PPC440EP_UART0_ADDR;
port.membase = ioremap64(PPC440EP_UART0_ADDR, 8);
port.irq = 0;
port.uartclk = clocks.uart0;
port.regshift = 0;
port.iotype = SERIAL_IO_MEM;
port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
port.line = 0;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 0 failed\n");
}
#if defined(CONFIG_SERIAL_TEXT_DEBUG)
/* Configure debug serial access */
gen550_init(0, &port);
#endif
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(0, &port);
#endif
port.mapbase = PPC440EP_UART1_ADDR;
port.membase = ioremap64(PPC440EP_UART1_ADDR, 8);
port.irq = 1;
port.uartclk = clocks.uart1;
port.line = 1;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 1 failed\n");
}
#if defined(CONFIG_SERIAL_TEXT_DEBUG)
/* Configure debug serial access */
gen550_init(1, &port);
#endif
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(1, &port);
#endif
}
int roach_late_iic_init(void)
{
if (!(roach_late_iic_base = ioremap64(EPX_IIC0_BASE, 0x100))){
return -1;
}
setreg(IIC0_INTRMSK, 0);
setreg(IIC0_MDCTRL, 0);
return 0;
}
static void __init
p3p440_setup_hose(void)
{
struct pci_controller *hose;
if (!is_monarch()) {
/*
* REMARK: This Non-Monarch mode need perhaps some changes.
* It's not tested at all, because of lack of hardware. --sr
*/
printk("P3P440-PCI: Non-Monarch detected, skipping PCI init!\n");
return;
}
/* Configure windows on the PCI-X host bridge */
p3p440_setup_pcix();
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = P3P440_PCI_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
P3P440_PCI_LOWER_IO,
P3P440_PCI_UPPER_IO,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
P3P440_PCI_LOWER_MEM,
P3P440_PCI_UPPER_MEM,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = P3P440_PCI_LOWER_IO;
hose->io_space.end = P3P440_PCI_UPPER_IO;
hose->mem_space.start = P3P440_PCI_LOWER_MEM;
hose->mem_space.end = P3P440_PCI_UPPER_MEM;
hose->io_base_virt = ioremap64(P3P440_PCI_IO_BASE, P3P440_PCI_IO_SIZE);
isa_io_base = (unsigned long)hose->io_base_virt;
setup_indirect_pci(hose, PCIX0_CFGA, PCIX0_CFGD);
hose->set_cfg_type = 1;
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = p3p440_map_irq;
}
static void __init
ocotea_early_serial_map(void)
{
struct uart_port port;
/* Setup ioremapped serial port access */
memset(&port, 0, sizeof(port));
port.membase = ioremap64(PPC440GX_UART0_ADDR, 8);
port.irq = UART0_INT;
port.uartclk = clocks.uart0;
port.regshift = 0;
port.iotype = UPIO_MEM;
port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
port.line = 0;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 0 failed\n");
}
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
/* Configure debug serial access */
gen550_init(0, &port);
/* Purge TLB entry added in head_44x.S for early serial access */
_tlbie(UART0_IO_BASE, 0);
#endif
port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
port.irq = UART1_INT;
port.uartclk = clocks.uart1;
port.line = 1;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 1 failed\n");
}
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
/* Configure debug serial access */
gen550_init(1, &port);
#endif
}
static void __init
yosemite_setup_arch(void)
{
uint32_t* gpio_base;
/* configuring GPIO1 for external interrupts */
gpio_base = (uint32_t*)ioremap64(PPC440EP_GPIO1_ADDR,
PPC440EP_GPIO_SIZE);
if (gpio_base) {
/* GPIO1_TCR reset bits 8-16*/
gpio_base[1] &= 0xff007fff;
/* GPIO1_TSRL reset bits 16-31*/
gpio_base[4] &= 0xffff0000;
/* GPIO1_ISR1L set bit pairs 16-17 to 30-31 to 01b*/
gpio_base[12] |= 0x5555;
/* GPIO1_TSRH reset bits 0-1*/
gpio_base[5] &= 0x3fffffff;
/* GPIO1_ISR1H set bit pair 0-1 to 01b*/
gpio_base[13] |= 0x40000000;
iounmap(gpio_base);
}
/* setting esxternal clk source for serial ports */
SDR_WRITE(DCRN_SDR_UART0, 0x800001);
SDR_WRITE(DCRN_SDR_UART1, 0x800001);
yosemite_set_emacdata();
ibm440gx_get_clocks(&clocks, YOSEMITE_SYSCLK, 6 * 1843200);
ocp_sys_info.opb_bus_freq = clocks.opb;
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Setup PCI host bridge */
yosemite_setup_hose();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA1;
#endif
yosemite_early_serial_map();
/* Identify the system */
printk( "AMCC PowerPC " BOARDNAME " Platform\n" );
}
static void __init
ocotea_early_serial_map(void)
{
struct serial_struct serial_req;
/* Setup ioremapped serial port access */
memset(&serial_req, 0, sizeof(serial_req));
serial_req.line = 0;
serial_req.baud_base = BASE_BAUD;
serial_req.port = 0;
serial_req.irq = 0;
serial_req.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
serial_req.io_type = SERIAL_IO_MEM;
serial_req.iomem_base = ioremap64(PPC440GX_UART0_ADDR, 8);
serial_req.iomem_reg_shift = 0;
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
/* Configure debug serial access */
gen550_init(0, &serial_req);
#endif
if (early_serial_setup(&serial_req) != 0) {
printk("Early serial init of port 0 failed\n");
}
/* Assume early_serial_setup() doesn't modify serial_req */
serial_req.line = 1;
serial_req.port = 1;
serial_req.irq = 1;
serial_req.iomem_base = ioremap64(PPC440GX_UART1_ADDR, 8);
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
/* Configure debug serial access */
gen550_init(1, &serial_req);
#endif
if (early_serial_setup(&serial_req) != 0) {
printk("Early serial init of port 1 failed\n");
}
}
static int is_monarch(void)
{
void __iomem *gpio_base;
ulong val;
gpio_base = ioremap64(GPIO_BASE, 0x1000);
val = in_be32((void *)(gpio_base+0x1c));
iounmap((void *)gpio_base);
if (val & CFG_MONARCH_IO)
return 0;
else
return 1;
}
static void __init
yucca_early_serial_map(void)
{
struct uart_port port;
/* Setup ioremapped serial port access */
memset(&port, 0, sizeof(port));
port.membase = ioremap64(PPC440SPE_UART0_ADDR, 8);
port.irq = UART0_INT;
port.uartclk = clocks.uart0;
port.regshift = 0;
port.iotype = UPIO_MEM;
port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
port.line = 0;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 0 failed\n");
}
port.membase = ioremap64(PPC440SPE_UART1_ADDR, 8);
port.irq = UART1_INT;
port.uartclk = clocks.uart1;
port.line = 1;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 1 failed\n");
}
port.membase = ioremap64(PPC440SPE_UART2_ADDR, 8);
port.irq = UART2_INT;
port.uartclk = BASE_BAUD;
port.line = 2;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 2 failed\n");
}
}
static void __init
ebony_setup_hose(void)
{
struct pci_controller *hose;
/* Configure windows on the PCI-X host bridge */
ebony_setup_pcix();
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
EBONY_PCI_LOWER_IO,
EBONY_PCI_UPPER_IO,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
EBONY_PCI_LOWER_MEM,
EBONY_PCI_UPPER_MEM,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = EBONY_PCI_LOWER_IO;
hose->io_space.end = EBONY_PCI_UPPER_IO;
hose->mem_space.start = EBONY_PCI_LOWER_MEM;
hose->mem_space.end = EBONY_PCI_UPPER_MEM;
isa_io_base =
(unsigned long)ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
hose->io_base_virt = (void *)isa_io_base;
setup_indirect_pci(hose,
EBONY_PCI_CFGA_PLB32,
EBONY_PCI_CFGD_PLB32);
hose->set_cfg_type = 1;
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = ebony_map_irq;
}
static int __init yucca_pcie_card_present(int port)
{
void __iomem *pcie_fpga_base;
u16 reg;
pcie_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE);
reg = in_be16(pcie_fpga_base + FPGA_REG1C);
iounmap(pcie_fpga_base);
switch(port) {
case 0: return !(reg & FPGA_REG1C_PE0_PRSNT);
case 1: return !(reg & FPGA_REG1C_PE1_PRSNT);
case 2: return !(reg & FPGA_REG1C_PE2_PRSNT);
default: return 0;
}
}
static void __init
ocotea_setup_arch(void)
{
ocotea_set_emacdata();
ibm440gx_tah_enable();
/*
* Determine various clocks.
* To be completely correct we should get SysClk
* from FPGA, because it can be changed by on-board switches
* --ebs
*/
ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
ocp_sys_info.opb_bus_freq = clocks.opb;
/* Setup TODC access */
TODC_INIT(TODC_TYPE_DS1743,
0,
0,
ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE),
8);
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Setup PCI host bridge */
ocotea_setup_hose();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA1;
#endif
ocotea_early_serial_map();
/* Identify the system */
printk("IBM Ocotea port (MontaVista Software, Inc. <*****@*****.**>)\n");
}
static void __init
luan_setup_pcix(void)
{
int i;
void *pcix_reg_base;
for (i=0; i<3; i++) {
pcix_reg_base = ioremap64(PCIX0_REG_BASE + i * PCIX_REG_OFFSET,
PCIX_REG_SIZE);
/* Disable all windows */
PCIX_WRITEL(0, PCIX0_POM0SA);
PCIX_WRITEL(0, PCIX0_POM1SA);
PCIX_WRITEL(0, PCIX0_POM2SA);
PCIX_WRITEL(0, PCIX0_PIM0SA);
PCIX_WRITEL(0, PCIX0_PIM0SAH);
PCIX_WRITEL(0, PCIX0_PIM1SA);
PCIX_WRITEL(0, PCIX0_PIM2SA);
PCIX_WRITEL(0, PCIX0_PIM2SAH);
/*
* Setup 512MB PLB->PCI outbound mem window
* (a_n000_0000->0_n000_0000)
* */
PCIX_WRITEL(0x0000000a, PCIX0_POM0LAH);
PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0LAL);
PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0PCIAL);
PCIX_WRITEL(0xe0000001, PCIX0_POM0SA);
/* Setup 512MB PCI->PLB inbound memory window at 0, enable MSIs */
PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA);
PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH);
/* Enable PCIX0 I/O, Mem, and Busmaster cycles */
PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO |
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
iounmap(pcix_reg_base);
}
eieio();
}
static void __init
ppc440spe_setup_pcix(struct pci_controller *hose)
{
void *pcix_reg_base;
pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
/* Disable all windows */
PCIX_WRITEL(0, PCIX0_POM0SA);
PCIX_WRITEL(0, PCIX0_POM1SA);
PCIX_WRITEL(0, PCIX0_POM2SA);
PCIX_WRITEL(0, PCIX0_PIM0SA);
PCIX_WRITEL(0, PCIX0_PIM0SAH);
PCIX_WRITEL(0, PCIX0_PIM1SA);
PCIX_WRITEL(0, PCIX0_PIM2SA);
PCIX_WRITEL(0, PCIX0_PIM2SAH);
/*
* Setup 512MB PLB->PCI outbound mem window
* (a_n000_0000->0_n000_0000)
* */
PCIX_WRITEL(0x0000000d, PCIX0_POM0LAH);
PCIX_WRITEL(hose->mem_space.start, PCIX0_POM0LAL);
PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
PCIX_WRITEL(hose->mem_space.start, PCIX0_POM0PCIAL);
PCIX_WRITEL(~(hose->mem_space.end - hose->mem_space.start) | 1 ,
PCIX0_POM0SA);
/* Setup 1GB PCI->PLB inbound memory window at 0, enable MSIs */
PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
PCIX_WRITEL(0xc0000007, PCIX0_PIM0SA);
PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH);
/* Enable PCIX0 I/O, Mem, and Busmaster cycles */
PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER, PCIX0_COMMAND);
iounmap(pcix_reg_base);
eieio();
}
static void __init
bamboo_setup_arch(void)
{
bamboo_set_emacdata();
ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
ocp_sys_info.opb_bus_freq = clocks.opb;
/* Setup TODC access */
TODC_INIT(TODC_TYPE_DS1743,
0,
0,
ioremap64(BAMBOO_RTC_ADDR, BAMBOO_RTC_SIZE),
8);
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Setup PCI host bridge */
bamboo_setup_hose();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA1;
#endif
bamboo_early_serial_map();
/* Identify the system */
printk("IBM Bamboo port (MontaVista Software, Inc. ([email protected]))\n");
}
static void __init
luan_setup_hose(struct pci_controller *hose,
int lower_mem,
int upper_mem,
int cfga,
int cfgd,
u64 pcix_io_base)
{
char name[20];
sprintf(name, "PCIX%d host bridge", hose->index);
hose->pci_mem_offset = LUAN_PCIX_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
LUAN_PCIX_LOWER_IO,
LUAN_PCIX_UPPER_IO,
IORESOURCE_IO,
name);
pci_init_resource(&hose->mem_resources[0],
lower_mem,
upper_mem,
IORESOURCE_MEM,
name);
hose->io_space.start = LUAN_PCIX_LOWER_IO;
hose->io_space.end = LUAN_PCIX_UPPER_IO;
hose->mem_space.start = lower_mem;
hose->mem_space.end = upper_mem;
isa_io_base =
(unsigned long)ioremap64(pcix_io_base, PCIX_IO_SIZE);
hose->io_base_virt = (void *)isa_io_base;
setup_indirect_pci(hose, cfga, cfgd);
hose->set_cfg_type = 1;
}
static void __init
ocotea_setup_arch(void)
{
ocotea_set_emacdata();
ibm440gx_tah_enable();
/* Setup TODC access */
TODC_INIT(TODC_TYPE_DS1743,
0,
0,
ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE),
8);
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Setup PCI host bridge */
ocotea_setup_hose();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA1;
#endif
ocotea_early_serial_map();
/* Identify the system */
printk("IBM Ocotea port (MontaVista Software, Inc. <*****@*****.**>)\n");
}
int __init init_ebony(void)
{
u8 fpga0_reg;
u8 __iomem *fpga0_adr;
unsigned long long small_flash_base, large_flash_base;
fpga0_adr = ioremap64(EBONY_FPGA_ADDR, 16);
if (!fpga0_adr)
return -ENOMEM;
fpga0_reg = readb(fpga0_adr);
iounmap(fpga0_adr);
if (EBONY_BOOT_SMALL_FLASH(fpga0_reg) &&
!EBONY_FLASH_SEL(fpga0_reg))
small_flash_base = EBONY_SMALL_FLASH_HIGH2;
else if (EBONY_BOOT_SMALL_FLASH(fpga0_reg) &&
EBONY_FLASH_SEL(fpga0_reg))
small_flash_base = EBONY_SMALL_FLASH_HIGH1;
else if (!EBONY_BOOT_SMALL_FLASH(fpga0_reg) &&
!EBONY_FLASH_SEL(fpga0_reg))
small_flash_base = EBONY_SMALL_FLASH_LOW2;
else
small_flash_base = EBONY_SMALL_FLASH_LOW1;
if (EBONY_BOOT_SMALL_FLASH(fpga0_reg) &&
!EBONY_ONBRD_FLASH_EN(fpga0_reg))
large_flash_base = EBONY_LARGE_FLASH_LOW;
else
large_flash_base = EBONY_LARGE_FLASH_HIGH;
ebony_small_map.phys = small_flash_base;
ebony_small_map.virt = ioremap64(small_flash_base,
ebony_small_map.size);
if (!ebony_small_map.virt) {
printk("Failed to ioremap flash\n");
return -EIO;
}
simple_map_init(&ebony_small_map);
flash = do_map_probe("jedec_probe", &ebony_small_map);
if (flash) {
flash->owner = THIS_MODULE;
add_mtd_partitions(flash, ebony_small_partitions,
ARRAY_SIZE(ebony_small_partitions));
} else {
printk("map probe failed for flash\n");
return -ENXIO;
}
ebony_large_map.phys = large_flash_base;
ebony_large_map.virt = ioremap64(large_flash_base,
ebony_large_map.size);
if (!ebony_large_map.virt) {
printk("Failed to ioremap flash\n");
return -EIO;
}
simple_map_init(&ebony_large_map);
flash = do_map_probe("jedec_probe", &ebony_large_map);
if (flash) {
flash->owner = THIS_MODULE;
add_mtd_partitions(flash, ebony_large_partitions,
ARRAY_SIZE(ebony_large_partitions));
} else {
printk("map probe failed for flash\n");
return -ENXIO;
}
return 0;
}
static int bamboo_setup_flash(void)
{
u8 setting_reg;
u8 *setting_adr;
unsigned long *gpio_base;
setting_adr = ioremap64(BAMBOO_FPGA_SETTING_REG_ADDR, 8);
if (!setting_adr)
return -ENOMEM;
setting_reg = readb(setting_adr);
iounmap(setting_adr);
/* Some versions of PIBS don't set up the GPIO controller
for the devices on chip select 4 (large flash and sram). */
gpio_base = ioremap64(0xEF600B00ULL, 0x80);
if (!gpio_base) {
printk(KERN_ERR "Failed to ioremap GPIO\n");
return -ENOMEM;
}
*(gpio_base + 0x02) |= 0x00001000;
*(gpio_base + 0x04) |= 0x00001000;
iounmap(gpio_base);
if (!BAMBOO_BOOT_NAND_FLASH(setting_reg)) {
if (BAMBOO_BOOT_SMALL_FLASH(setting_reg)) {
bamboo_small_nor.start = BAMBOO_SMALL_FLASH_HIGH;
bamboo_small_nor.end = BAMBOO_SMALL_FLASH_HIGH +
BAMBOO_SMALL_FLASH_SIZE-1;
}
platform_device_register(&bamboo_small_nor_device);
}
if (BAMBOO_BOOT_NAND_FLASH(setting_reg) ||
BAMBOO_BOOT_SMALL_FLASH(setting_reg)) {
} else if (BAMBOO_LARGE_FLASH_EN(setting_reg)) {
bamboo_large_nor.start = BAMBOO_LARGE_FLASH_HIGH1;
bamboo_large_nor.end = BAMBOO_LARGE_FLASH_HIGH1 +
BAMBOO_LARGE_FLASH_SIZE;
bamboo_sram.start = BAMBOO_SRAM_HIGH2;
bamboo_sram.end = BAMBOO_SRAM_HIGH2 + BAMBOO_SRAM_SIZE;
} else {
bamboo_large_nor.start = BAMBOO_LARGE_FLASH_HIGH2;
bamboo_large_nor.end = BAMBOO_LARGE_FLASH_HIGH2 +
BAMBOO_LARGE_FLASH_SIZE;
bamboo_sram.start = BAMBOO_SRAM_HIGH1;
bamboo_sram.end = BAMBOO_SRAM_HIGH1 + BAMBOO_SRAM_SIZE;
}
platform_device_register(&bamboo_large_nor_device);
platform_device_register(&bamboo_sram_device);
platform_device_register(&bamboo_ndfc_device);
platform_device_register(&bamboo_nand_device);
printk(KERN_DEBUG "small: %08x %08x\n",
bamboo_small_nor.start, bamboo_small_nor.end);
printk(KERN_DEBUG "large: %08x %08x\n", bamboo_large_nor.start, bamboo_large_nor.end);
printk(KERN_DEBUG "sram: %08x %08x\n", bamboo_sram.start, bamboo_sram.end);
return 0;
}
static void __init
bamboo_early_serial_map(void)
{
struct uart_port port;
/* Setup ioremapped serial port access */
memset(&port, 0, sizeof(port));
port.membase = ioremap64(PPC440EP_UART0_ADDR, 8);
port.irq = 0;
port.uartclk = clocks.uart0;
port.regshift = 0;
port.iotype = UPIO_MEM;
port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
port.line = 0;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 0 failed\n");
}
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
/* Configure debug serial access */
gen550_init(0, &port);
#endif
port.membase = ioremap64(PPC440EP_UART1_ADDR, 8);
port.irq = 1;
port.uartclk = clocks.uart1;
port.line = 1;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 1 failed\n");
}
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
/* Configure debug serial access */
gen550_init(1, &port);
#endif
port.membase = ioremap64(PPC440EP_UART2_ADDR, 8);
port.irq = 3;
port.uartclk = clocks.uart2;
port.line = 2;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 2 failed\n");
}
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
/* Configure debug serial access */
gen550_init(2, &port);
#endif
port.membase = ioremap64(PPC440EP_UART3_ADDR, 8);
port.irq = 4;
port.uartclk = clocks.uart3;
port.line = 3;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 3 failed\n");
}
}
static void __init
bamboo_setup_pci(void)
{
void *pci_reg_base;
unsigned long memory_size;
memory_size = ppc_md.find_end_of_memory();
pci_reg_base = ioremap64(BAMBOO_PCIL0_BASE, BAMBOO_PCIL0_SIZE);
/* Enable PCI I/O, Mem, and Busmaster cycles */
PCI_WRITEW(PCI_READW(PCI_COMMAND) |
PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER, PCI_COMMAND);
/* Disable region first */
PCI_WRITEL(0, BAMBOO_PCIL0_PMM0MA);
/* PLB starting addr: 0x00000000A0000000 */
PCI_WRITEL(BAMBOO_PCI_PHY_MEM_BASE, BAMBOO_PCIL0_PMM0LA);
/* PCI start addr, 0xA0000000 (PCI Address) */
PCI_WRITEL(BAMBOO_PCI_MEM_BASE, BAMBOO_PCIL0_PMM0PCILA);
PCI_WRITEL(0, BAMBOO_PCIL0_PMM0PCIHA);
/* Enable no pre-fetch, enable region */
PCI_WRITEL(((0xffffffff -
(BAMBOO_PCI_UPPER_MEM - BAMBOO_PCI_MEM_BASE)) | 0x01),
BAMBOO_PCIL0_PMM0MA);
/* Disable region one */
PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
PCI_WRITEL(0, BAMBOO_PCIL0_PMM1LA);
PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCILA);
PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCIHA);
PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
/* Disable region two */
PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
PCI_WRITEL(0, BAMBOO_PCIL0_PMM2LA);
PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCILA);
PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCIHA);
PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
/* Now configure the PCI->PLB windows, we only use PTM1
*
* For Inbound flow, set the window size to all available memory
* This is required because if size is smaller,
* then Eth/PCI DD would fail as PCI card not able to access
* the memory allocated by DD.
*/
PCI_WRITEL(0, BAMBOO_PCIL0_PTM1MS); /* disabled region 1 */
PCI_WRITEL(0, BAMBOO_PCIL0_PTM1LA); /* begin of address map */
memory_size = 1 << fls(memory_size - 1);
/* Size low + Enabled */
PCI_WRITEL((0xffffffff - (memory_size - 1)) | 0x1, BAMBOO_PCIL0_PTM1MS);
eieio();
iounmap(pci_reg_base);
}
