static void
assemble_variant(struct ir3_shader_variant *v)
{
struct fd_context *ctx = fd_context(v->shader->pctx);
uint32_t sz, *bin;
bin = ir3_assemble(v->ir, &v->info, ctx->screen->gpu_id);
sz = v->info.sizedwords * 4;
v->bo = fd_bo_new(ctx->dev, sz,
DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
DRM_FREEDRENO_GEM_TYPE_KMEM);
memcpy(fd_bo_map(v->bo), bin, sz);
free(bin);
if (ctx->screen->gpu_id >= 400) {
v->instrlen = v->info.sizedwords / (2 * 16);
} else {
v->instrlen = v->info.sizedwords / (2 * 4);
}
/* NOTE: if relative addressing is used, we set constlen in
* the compiler (to worst-case value) since we don't know in
* the assembler what the max addr reg value can be:
*/
v->constlen = MAX2(v->constlen, v->info.max_const + 1);
/* no need to keep the ir around beyond this point: */
ir3_destroy(v->ir);
v->ir = NULL;
}
static void
assemble_variant(struct ir3_shader_variant *v)
{
struct fd_context *ctx = fd_context(v->shader->pctx);
uint32_t sz, *bin;
bin = ir3_assemble(v->ir, &v->info);
sz = v->info.sizedwords * 4;
v->bo = fd_bo_new(ctx->dev, sz,
DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
DRM_FREEDRENO_GEM_TYPE_KMEM);
memcpy(fd_bo_map(v->bo), bin, sz);
free(bin);
v->instrlen = v->info.sizedwords / 8;
/* NOTE: if relative addressing is used, we set constlen in
* the compiler (to worst-case value) since we don't know in
* the assembler what the max addr reg value can be:
*/
v->constlen = MAX2(v->constlen, v->info.max_const + 1);
}
static void dump_info(struct ir3_shader_variant *so, const char *str)
{
struct ir3_info info;
uint32_t *bin;
const char *type = (so->type == SHADER_VERTEX) ? "VERT" : "FRAG";
// for debug, dump some before/after info:
bin = ir3_assemble(so->ir, &info);
if (fd_mesa_debug & FD_DBG_DISASM) {
struct ir3_block *block = so->ir->block;
unsigned i;
debug_printf("; %s: %s\n", type, str);
for (i = 0; i < block->ninputs; i++) {
uint8_t regid;
if (!block->inputs[i])
continue;
regid = block->inputs[i]->regs[0]->num;
debug_printf("@in(r%d.%c)\tin%d\n",
(regid >> 2), "xyzw"[regid & 0x3], i);
}
for (i = 0; i < block->noutputs; i++) {
uint8_t regid;
if (!block->outputs[i])
continue;
/* kill shows up as a virtual output.. skip it! */
if (is_kill(block->outputs[i]))
continue;
regid = block->outputs[i]->regs[0]->num;
debug_printf("@out(r%d.%c)\tout%d\n",
(regid >> 2), "xyzw"[regid & 0x3], i);
}
disasm_a3xx(bin, info.sizedwords, 0, so->type);
debug_printf("; %s: outputs:", type);
for (i = 0; i < so->outputs_count; i++) {
uint8_t regid = so->outputs[i].regid;
ir3_semantic sem = so->outputs[i].semantic;
debug_printf(" r%d.%c (%u:%u)",
(regid >> 2), "xyzw"[regid & 0x3],
sem2name(sem), sem2idx(sem));
}
debug_printf("\n");
debug_printf("; %s: inputs:", type);
for (i = 0; i < so->inputs_count; i++) {
uint8_t regid = so->inputs[i].regid;
ir3_semantic sem = so->inputs[i].semantic;
debug_printf(" r%d.%c (%u:%u,cm=%x,il=%u,b=%u)",
(regid >> 2), "xyzw"[regid & 0x3],
sem2name(sem), sem2idx(sem),
so->inputs[i].compmask,
so->inputs[i].inloc,
so->inputs[i].bary);
}
debug_printf("\n");
}
debug_printf("; %s: %u instructions, %d half, %d full\n\n",
type, info.instrs_count, info.max_half_reg + 1, info.max_reg + 1);
free(bin);
}
